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| author | Elvin Li <elvin.li@intel.com> | 2013-10-09 08:30:59 +0000 |
|---|---|---|
| committer | li-elvin <li-elvin@6f19259b-4bc3-4df7-8a09-765794883524> | 2013-10-09 08:30:59 +0000 |
| commit | 5bcb62a4098c9bde9be6af0833a025adc768e08d (patch) | |
| tree | aea7df61e6a61c6f0f43b19c58206adea8de3364 /MdeModulePkg/Bus/Pci/XhciDxe/XhciReg.h | |
| parent | 980f3026e56ef7868962bbca386655f11c10fd33 (diff) | |
| download | edk2-5bcb62a4098c9bde9be6af0833a025adc768e08d.zip edk2-5bcb62a4098c9bde9be6af0833a025adc768e08d.tar.gz edk2-5bcb62a4098c9bde9be6af0833a025adc768e08d.tar.bz2 | |
Just like EhciDxe, do not reset host controller when debug capability is enabled in XhciDxe driver.
Signed-off-by: Elvin Li <elvin.li@intel.com>
Reviewed-by: Feng Tian <feng.tian@intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14760 6f19259b-4bc3-4df7-8a09-765794883524
Diffstat (limited to 'MdeModulePkg/Bus/Pci/XhciDxe/XhciReg.h')
| -rw-r--r-- | MdeModulePkg/Bus/Pci/XhciDxe/XhciReg.h | 31 |
1 files changed, 28 insertions, 3 deletions
diff --git a/MdeModulePkg/Bus/Pci/XhciDxe/XhciReg.h b/MdeModulePkg/Bus/Pci/XhciDxe/XhciReg.h index eea468b..20a5510 100644 --- a/MdeModulePkg/Bus/Pci/XhciDxe/XhciReg.h +++ b/MdeModulePkg/Bus/Pci/XhciDxe/XhciReg.h @@ -29,6 +29,9 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. #define USB_HUB_CLASS_CODE 0x09
#define USB_HUB_SUBCLASS_CODE 0x00
+#define XHC_CAP_USB_LEGACY 0x01
+#define XHC_CAP_USB_DEBUG 0x0A
+
//============================================//
// XHCI register offset //
//============================================//
@@ -67,6 +70,11 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. #define XHC_ERSTBA_OFFSET 0x30 // Event Ring Segment Table Base Address Register Offset
#define XHC_ERDP_OFFSET 0x38 // Event Ring Dequeue Pointer Register Offset
+//
+// Debug registers offset
+//
+#define XHC_DC_DCCTRL 0x20
+
#define USBLEGSP_BIOS_SEMAPHORE BIT16 // HC BIOS Owned Semaphore
#define USBLEGSP_OS_SEMAPHORE BIT24 // HC OS Owned Semaphore
@@ -448,6 +456,21 @@ XhcClearRuntimeRegBit ( );
/**
+ Read XHCI extended capability register.
+
+ @param Xhc The XHCI Instance.
+ @param Offset The offset of the extended capability register.
+
+ @return The register content read
+
+**/
+UINT32
+XhcReadExtCapReg (
+ IN USB_XHCI_INSTANCE *Xhc,
+ IN UINT32 Offset
+ );
+
+/**
Whether the XHCI host controller is halted.
@param Xhc The XHCI Instance.
@@ -524,16 +547,18 @@ XhcRunHC ( );
/**
- Calculate the XHCI legacy support capability register offset.
+ Calculate the offset of the XHCI capability.
@param Xhc The XHCI Instance.
+ @param CapId The XHCI Capability ID.
@return The offset of XHCI legacy support capability register.
**/
UINT32
-XhcGetLegSupCapAddr (
- IN USB_XHCI_INSTANCE *Xhc
+XhcGetCapabilityAddr (
+ IN USB_XHCI_INSTANCE *Xhc,
+ IN UINT8 CapId
);
#endif
|