diff options
| author | Michael Kubacki <michael.kubacki@microsoft.com> | 2021-12-05 14:54:02 -0800 |
|---|---|---|
| committer | mergify[bot] <37929162+mergify[bot]@users.noreply.github.com> | 2021-12-07 17:24:28 +0000 |
| commit | 1436aea4d5707e672672a11bda72be2c63c936c3 (patch) | |
| tree | 370c9d5bd8823aa8ea7bce71a0f29bff71feff67 /MdeModulePkg/Bus/Pci/PciHostBridgeDxe | |
| parent | 7c7184e201a90a1d2376e615e55e3f4074731468 (diff) | |
| download | edk2-1436aea4d5707e672672a11bda72be2c63c936c3.zip edk2-1436aea4d5707e672672a11bda72be2c63c936c3.tar.gz edk2-1436aea4d5707e672672a11bda72be2c63c936c3.tar.bz2 | |
MdeModulePkg: Apply uncrustify changes
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3737
Apply uncrustify changes to .c/.h files in the MdeModulePkg package
Cc: Andrew Fish <afish@apple.com>
Cc: Leif Lindholm <leif@nuviainc.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Signed-off-by: Michael Kubacki <michael.kubacki@microsoft.com>
Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
Diffstat (limited to 'MdeModulePkg/Bus/Pci/PciHostBridgeDxe')
5 files changed, 1169 insertions, 931 deletions
diff --git a/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridge.c b/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridge.c index 5c8f0f4..b20bcd3 100644 --- a/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridge.c +++ b/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridge.c @@ -11,18 +11,18 @@ SPDX-License-Identifier: BSD-2-Clause-Patent #include "PciRootBridge.h"
#include "PciHostResource.h"
-EFI_CPU_IO2_PROTOCOL *mCpuIo;
+EFI_CPU_IO2_PROTOCOL *mCpuIo;
-GLOBAL_REMOVE_IF_UNREFERENCED CHAR16 *mAcpiAddressSpaceTypeStr[] = {
+GLOBAL_REMOVE_IF_UNREFERENCED CHAR16 *mAcpiAddressSpaceTypeStr[] = {
L"Mem", L"I/O", L"Bus"
};
-GLOBAL_REMOVE_IF_UNREFERENCED CHAR16 *mPciResourceTypeStr[] = {
+GLOBAL_REMOVE_IF_UNREFERENCED CHAR16 *mPciResourceTypeStr[] = {
L"I/O", L"Mem", L"PMem", L"Mem64", L"PMem64", L"Bus"
};
-EDKII_IOMMU_PROTOCOL *mIoMmu;
-EFI_EVENT mIoMmuEvent;
-VOID *mIoMmuRegistration;
+EDKII_IOMMU_PROTOCOL *mIoMmu;
+EFI_EVENT mIoMmuEvent;
+VOID *mIoMmuRegistration;
/**
This routine gets translation offset from a root bridge instance by resource type.
@@ -34,8 +34,8 @@ VOID *mIoMmuRegistration; **/
UINT64
GetTranslationByResourceType (
- IN PCI_ROOT_BRIDGE_INSTANCE *RootBridge,
- IN PCI_RESOURCE_TYPE ResourceType
+ IN PCI_ROOT_BRIDGE_INSTANCE *RootBridge,
+ IN PCI_RESOURCE_TYPE ResourceType
)
{
switch (ResourceType) {
@@ -92,22 +92,24 @@ GetTranslationByResourceType ( **/
EFI_STATUS
IntersectIoDescriptor (
- IN UINT64 Base,
- IN UINT64 Length,
- IN CONST EFI_GCD_IO_SPACE_DESCRIPTOR *Descriptor
+ IN UINT64 Base,
+ IN UINT64 Length,
+ IN CONST EFI_GCD_IO_SPACE_DESCRIPTOR *Descriptor
)
{
- UINT64 IntersectionBase;
- UINT64 IntersectionEnd;
- EFI_STATUS Status;
+ UINT64 IntersectionBase;
+ UINT64 IntersectionEnd;
+ EFI_STATUS Status;
if (Descriptor->GcdIoType == EfiGcdIoTypeIo) {
return EFI_SUCCESS;
}
IntersectionBase = MAX (Base, Descriptor->BaseAddress);
- IntersectionEnd = MIN (Base + Length,
- Descriptor->BaseAddress + Descriptor->Length);
+ IntersectionEnd = MIN (
+ Base + Length,
+ Descriptor->BaseAddress + Descriptor->Length
+ );
if (IntersectionBase >= IntersectionEnd) {
//
// The descriptor and the aperture don't overlap.
@@ -116,19 +118,36 @@ IntersectIoDescriptor ( }
if (Descriptor->GcdIoType == EfiGcdIoTypeNonExistent) {
- Status = gDS->AddIoSpace (EfiGcdIoTypeIo, IntersectionBase,
- IntersectionEnd - IntersectionBase);
+ Status = gDS->AddIoSpace (
+ EfiGcdIoTypeIo,
+ IntersectionBase,
+ IntersectionEnd - IntersectionBase
+ );
- DEBUG ((EFI_ERROR (Status) ? DEBUG_ERROR : DEBUG_VERBOSE,
- "%a: %a: add [%Lx, %Lx): %r\n", gEfiCallerBaseName, __FUNCTION__,
- IntersectionBase, IntersectionEnd, Status));
+ DEBUG ((
+ EFI_ERROR (Status) ? DEBUG_ERROR : DEBUG_VERBOSE,
+ "%a: %a: add [%Lx, %Lx): %r\n",
+ gEfiCallerBaseName,
+ __FUNCTION__,
+ IntersectionBase,
+ IntersectionEnd,
+ Status
+ ));
return Status;
}
- DEBUG ((DEBUG_ERROR, "%a: %a: desc [%Lx, %Lx) type %u conflicts with "
- "aperture [%Lx, %Lx)\n", gEfiCallerBaseName, __FUNCTION__,
- Descriptor->BaseAddress, Descriptor->BaseAddress + Descriptor->Length,
- (UINT32)Descriptor->GcdIoType, Base, Base + Length));
+ DEBUG ((
+ DEBUG_ERROR,
+ "%a: %a: desc [%Lx, %Lx) type %u conflicts with "
+ "aperture [%Lx, %Lx)\n",
+ gEfiCallerBaseName,
+ __FUNCTION__,
+ Descriptor->BaseAddress,
+ Descriptor->BaseAddress + Descriptor->Length,
+ (UINT32)Descriptor->GcdIoType,
+ Base,
+ Base + Length
+ ));
return EFI_INVALID_PARAMETER;
}
@@ -144,19 +163,24 @@ IntersectIoDescriptor ( **/
EFI_STATUS
AddIoSpace (
- IN UINT64 Base,
- IN UINT64 Length
+ IN UINT64 Base,
+ IN UINT64 Length
)
{
- EFI_STATUS Status;
- UINTN Index;
- UINTN NumberOfDescriptors;
- EFI_GCD_IO_SPACE_DESCRIPTOR *IoSpaceMap;
+ EFI_STATUS Status;
+ UINTN Index;
+ UINTN NumberOfDescriptors;
+ EFI_GCD_IO_SPACE_DESCRIPTOR *IoSpaceMap;
Status = gDS->GetIoSpaceMap (&NumberOfDescriptors, &IoSpaceMap);
if (EFI_ERROR (Status)) {
- DEBUG ((DEBUG_ERROR, "%a: %a: GetIoSpaceMap(): %r\n",
- gEfiCallerBaseName, __FUNCTION__, Status));
+ DEBUG ((
+ DEBUG_ERROR,
+ "%a: %a: GetIoSpaceMap(): %r\n",
+ gEfiCallerBaseName,
+ __FUNCTION__,
+ Status
+ ));
return Status;
}
@@ -167,24 +191,26 @@ AddIoSpace ( }
}
- DEBUG_CODE_BEGIN ();
- //
- // Make sure there are adjacent descriptors covering [Base, Base + Length).
- // It is possible that they have not been merged; merging can be prevented
- // by allocation.
- //
- UINT64 CheckBase;
- EFI_STATUS CheckStatus;
- EFI_GCD_IO_SPACE_DESCRIPTOR Descriptor;
-
- for (CheckBase = Base;
- CheckBase < Base + Length;
- CheckBase = Descriptor.BaseAddress + Descriptor.Length) {
- CheckStatus = gDS->GetIoSpaceDescriptor (CheckBase, &Descriptor);
- ASSERT_EFI_ERROR (CheckStatus);
- ASSERT (Descriptor.GcdIoType == EfiGcdIoTypeIo);
- }
- DEBUG_CODE_END ();
+ DEBUG_CODE_BEGIN ();
+ //
+ // Make sure there are adjacent descriptors covering [Base, Base + Length).
+ // It is possible that they have not been merged; merging can be prevented
+ // by allocation.
+ //
+ UINT64 CheckBase;
+ EFI_STATUS CheckStatus;
+ EFI_GCD_IO_SPACE_DESCRIPTOR Descriptor;
+
+ for (CheckBase = Base;
+ CheckBase < Base + Length;
+ CheckBase = Descriptor.BaseAddress + Descriptor.Length)
+ {
+ CheckStatus = gDS->GetIoSpaceDescriptor (CheckBase, &Descriptor);
+ ASSERT_EFI_ERROR (CheckStatus);
+ ASSERT (Descriptor.GcdIoType == EfiGcdIoTypeIo);
+ }
+
+ DEBUG_CODE_END ();
FreeIoSpaceMap:
FreePool (IoSpaceMap);
@@ -233,24 +259,27 @@ FreeIoSpaceMap: **/
EFI_STATUS
IntersectMemoryDescriptor (
- IN UINT64 Base,
- IN UINT64 Length,
- IN UINT64 Capabilities,
- IN CONST EFI_GCD_MEMORY_SPACE_DESCRIPTOR *Descriptor
+ IN UINT64 Base,
+ IN UINT64 Length,
+ IN UINT64 Capabilities,
+ IN CONST EFI_GCD_MEMORY_SPACE_DESCRIPTOR *Descriptor
)
{
- UINT64 IntersectionBase;
- UINT64 IntersectionEnd;
- EFI_STATUS Status;
+ UINT64 IntersectionBase;
+ UINT64 IntersectionEnd;
+ EFI_STATUS Status;
- if (Descriptor->GcdMemoryType == EfiGcdMemoryTypeMemoryMappedIo &&
- (Descriptor->Capabilities & Capabilities) == Capabilities) {
+ if ((Descriptor->GcdMemoryType == EfiGcdMemoryTypeMemoryMappedIo) &&
+ ((Descriptor->Capabilities & Capabilities) == Capabilities))
+ {
return EFI_SUCCESS;
}
IntersectionBase = MAX (Base, Descriptor->BaseAddress);
- IntersectionEnd = MIN (Base + Length,
- Descriptor->BaseAddress + Descriptor->Length);
+ IntersectionEnd = MIN (
+ Base + Length,
+ Descriptor->BaseAddress + Descriptor->Length
+ );
if (IntersectionBase >= IntersectionEnd) {
//
// The descriptor and the aperture don't overlap.
@@ -259,21 +288,39 @@ IntersectMemoryDescriptor ( }
if (Descriptor->GcdMemoryType == EfiGcdMemoryTypeNonExistent) {
- Status = gDS->AddMemorySpace (EfiGcdMemoryTypeMemoryMappedIo,
- IntersectionBase, IntersectionEnd - IntersectionBase,
- Capabilities);
+ Status = gDS->AddMemorySpace (
+ EfiGcdMemoryTypeMemoryMappedIo,
+ IntersectionBase,
+ IntersectionEnd - IntersectionBase,
+ Capabilities
+ );
- DEBUG ((EFI_ERROR (Status) ? DEBUG_ERROR : DEBUG_VERBOSE,
- "%a: %a: add [%Lx, %Lx): %r\n", gEfiCallerBaseName, __FUNCTION__,
- IntersectionBase, IntersectionEnd, Status));
+ DEBUG ((
+ EFI_ERROR (Status) ? DEBUG_ERROR : DEBUG_VERBOSE,
+ "%a: %a: add [%Lx, %Lx): %r\n",
+ gEfiCallerBaseName,
+ __FUNCTION__,
+ IntersectionBase,
+ IntersectionEnd,
+ Status
+ ));
return Status;
}
- DEBUG ((DEBUG_ERROR, "%a: %a: desc [%Lx, %Lx) type %u cap %Lx conflicts "
- "with aperture [%Lx, %Lx) cap %Lx\n", gEfiCallerBaseName, __FUNCTION__,
- Descriptor->BaseAddress, Descriptor->BaseAddress + Descriptor->Length,
- (UINT32)Descriptor->GcdMemoryType, Descriptor->Capabilities,
- Base, Base + Length, Capabilities));
+ DEBUG ((
+ DEBUG_ERROR,
+ "%a: %a: desc [%Lx, %Lx) type %u cap %Lx conflicts "
+ "with aperture [%Lx, %Lx) cap %Lx\n",
+ gEfiCallerBaseName,
+ __FUNCTION__,
+ Descriptor->BaseAddress,
+ Descriptor->BaseAddress + Descriptor->Length,
+ (UINT32)Descriptor->GcdMemoryType,
+ Descriptor->Capabilities,
+ Base,
+ Base + Length,
+ Capabilities
+ ));
return EFI_INVALID_PARAMETER;
}
@@ -290,49 +337,60 @@ IntersectMemoryDescriptor ( **/
EFI_STATUS
AddMemoryMappedIoSpace (
- IN UINT64 Base,
- IN UINT64 Length,
- IN UINT64 Capabilities
+ IN UINT64 Base,
+ IN UINT64 Length,
+ IN UINT64 Capabilities
)
{
- EFI_STATUS Status;
- UINTN Index;
- UINTN NumberOfDescriptors;
- EFI_GCD_MEMORY_SPACE_DESCRIPTOR *MemorySpaceMap;
+ EFI_STATUS Status;
+ UINTN Index;
+ UINTN NumberOfDescriptors;
+ EFI_GCD_MEMORY_SPACE_DESCRIPTOR *MemorySpaceMap;
Status = gDS->GetMemorySpaceMap (&NumberOfDescriptors, &MemorySpaceMap);
if (EFI_ERROR (Status)) {
- DEBUG ((DEBUG_ERROR, "%a: %a: GetMemorySpaceMap(): %r\n",
- gEfiCallerBaseName, __FUNCTION__, Status));
+ DEBUG ((
+ DEBUG_ERROR,
+ "%a: %a: GetMemorySpaceMap(): %r\n",
+ gEfiCallerBaseName,
+ __FUNCTION__,
+ Status
+ ));
return Status;
}
for (Index = 0; Index < NumberOfDescriptors; Index++) {
- Status = IntersectMemoryDescriptor (Base, Length, Capabilities,
- &MemorySpaceMap[Index]);
+ Status = IntersectMemoryDescriptor (
+ Base,
+ Length,
+ Capabilities,
+ &MemorySpaceMap[Index]
+ );
if (EFI_ERROR (Status)) {
goto FreeMemorySpaceMap;
}
}
DEBUG_CODE_BEGIN ();
- //
- // Make sure there are adjacent descriptors covering [Base, Base + Length).
- // It is possible that they have not been merged; merging can be prevented
- // by allocation and different capabilities.
- //
- UINT64 CheckBase;
- EFI_STATUS CheckStatus;
- EFI_GCD_MEMORY_SPACE_DESCRIPTOR Descriptor;
-
- for (CheckBase = Base;
- CheckBase < Base + Length;
- CheckBase = Descriptor.BaseAddress + Descriptor.Length) {
- CheckStatus = gDS->GetMemorySpaceDescriptor (CheckBase, &Descriptor);
- ASSERT_EFI_ERROR (CheckStatus);
- ASSERT (Descriptor.GcdMemoryType == EfiGcdMemoryTypeMemoryMappedIo);
- ASSERT ((Descriptor.Capabilities & Capabilities) == Capabilities);
- }
+ //
+ // Make sure there are adjacent descriptors covering [Base, Base + Length).
+ // It is possible that they have not been merged; merging can be prevented
+ // by allocation and different capabilities.
+ //
+ UINT64 CheckBase;
+ EFI_STATUS CheckStatus;
+ EFI_GCD_MEMORY_SPACE_DESCRIPTOR Descriptor;
+
+ for (CheckBase = Base;
+ CheckBase < Base + Length;
+ CheckBase = Descriptor.BaseAddress + Descriptor.Length)
+ {
+ CheckStatus = gDS->GetMemorySpaceDescriptor (CheckBase, &Descriptor);
+ ASSERT_EFI_ERROR (CheckStatus);
+ ASSERT (Descriptor.GcdMemoryType == EfiGcdMemoryTypeMemoryMappedIo);
+ ASSERT ((Descriptor.Capabilities & Capabilities) == Capabilities);
+ }
+
DEBUG_CODE_END ();
FreeMemorySpaceMap:
@@ -351,14 +409,14 @@ FreeMemorySpaceMap: VOID
EFIAPI
IoMmuProtocolCallback (
- IN EFI_EVENT Event,
- IN VOID *Context
+ IN EFI_EVENT Event,
+ IN VOID *Context
)
{
- EFI_STATUS Status;
+ EFI_STATUS Status;
Status = gBS->LocateProtocol (&gEdkiiIoMmuProtocolGuid, NULL, (VOID **)&mIoMmu);
- if (!EFI_ERROR(Status)) {
+ if (!EFI_ERROR (Status)) {
gBS->CloseEvent (mIoMmuEvent);
}
}
@@ -377,28 +435,28 @@ IoMmuProtocolCallback ( EFI_STATUS
EFIAPI
InitializePciHostBridge (
- IN EFI_HANDLE ImageHandle,
- IN EFI_SYSTEM_TABLE *SystemTable
+ IN EFI_HANDLE ImageHandle,
+ IN EFI_SYSTEM_TABLE *SystemTable
)
{
- EFI_STATUS Status;
- PCI_HOST_BRIDGE_INSTANCE *HostBridge;
- PCI_ROOT_BRIDGE_INSTANCE *RootBridge;
- PCI_ROOT_BRIDGE *RootBridges;
- UINTN RootBridgeCount;
- UINTN Index;
- PCI_ROOT_BRIDGE_APERTURE *MemApertures[4];
- UINTN MemApertureIndex;
- BOOLEAN ResourceAssigned;
- LIST_ENTRY *Link;
- UINT64 HostAddress;
+ EFI_STATUS Status;
+ PCI_HOST_BRIDGE_INSTANCE *HostBridge;
+ PCI_ROOT_BRIDGE_INSTANCE *RootBridge;
+ PCI_ROOT_BRIDGE *RootBridges;
+ UINTN RootBridgeCount;
+ UINTN Index;
+ PCI_ROOT_BRIDGE_APERTURE *MemApertures[4];
+ UINTN MemApertureIndex;
+ BOOLEAN ResourceAssigned;
+ LIST_ENTRY *Link;
+ UINT64 HostAddress;
RootBridges = PciHostBridgeGetRootBridges (&RootBridgeCount);
if ((RootBridges == NULL) || (RootBridgeCount == 0)) {
return EFI_UNSUPPORTED;
}
- Status = gBS->LocateProtocol (&gEfiCpuIo2ProtocolGuid, NULL, (VOID **) &mCpuIo);
+ Status = gBS->LocateProtocol (&gEfiCpuIo2ProtocolGuid, NULL, (VOID **)&mCpuIo);
ASSERT_EFI_ERROR (Status);
//
@@ -407,10 +465,10 @@ InitializePciHostBridge ( HostBridge = AllocateZeroPool (sizeof (PCI_HOST_BRIDGE_INSTANCE));
ASSERT (HostBridge != NULL);
- HostBridge->Signature = PCI_HOST_BRIDGE_SIGNATURE;
- HostBridge->CanRestarted = TRUE;
+ HostBridge->Signature = PCI_HOST_BRIDGE_SIGNATURE;
+ HostBridge->CanRestarted = TRUE;
InitializeListHead (&HostBridge->RootBridges);
- ResourceAssigned = FALSE;
+ ResourceAssigned = FALSE;
//
// Create Root Bridge Device Handle in this Host Bridge
@@ -439,8 +497,10 @@ InitializePciHostBridge ( // Base and Limit in PCI_ROOT_BRIDGE_APERTURE are device address.
// For GCD resource manipulation, we need to use host address.
//
- HostAddress = TO_HOST_ADDRESS (RootBridges[Index].Io.Base,
- RootBridges[Index].Io.Translation);
+ HostAddress = TO_HOST_ADDRESS (
+ RootBridges[Index].Io.Base,
+ RootBridges[Index].Io.Translation
+ );
Status = AddIoSpace (
HostAddress,
@@ -478,8 +538,10 @@ InitializePciHostBridge ( // Base and Limit in PCI_ROOT_BRIDGE_APERTURE are device address.
// For GCD resource manipulation, we need to use host address.
//
- HostAddress = TO_HOST_ADDRESS (MemApertures[MemApertureIndex]->Base,
- MemApertures[MemApertureIndex]->Translation);
+ HostAddress = TO_HOST_ADDRESS (
+ MemApertures[MemApertureIndex]->Base,
+ MemApertures[MemApertureIndex]->Translation
+ );
Status = AddMemoryMappedIoSpace (
HostAddress,
MemApertures[MemApertureIndex]->Limit - MemApertures[MemApertureIndex]->Base + 1,
@@ -494,6 +556,7 @@ InitializePciHostBridge ( if (EFI_ERROR (Status)) {
DEBUG ((DEBUG_WARN, "PciHostBridge driver failed to set EFI_MEMORY_UC to MMIO aperture - %r.\n", Status));
}
+
if (ResourceAssigned) {
Status = gDS->AllocateMemorySpace (
EfiGcdAllocateAddress,
@@ -508,6 +571,7 @@ InitializePciHostBridge ( }
}
}
+
//
// Insert Root Bridge Handle Instance
//
@@ -519,18 +583,19 @@ InitializePciHostBridge ( // PciHostBridgeResourceAllocation protocol.
//
if (!ResourceAssigned) {
- HostBridge->ResAlloc.NotifyPhase = NotifyPhase;
- HostBridge->ResAlloc.GetNextRootBridge = GetNextRootBridge;
- HostBridge->ResAlloc.GetAllocAttributes = GetAttributes;
- HostBridge->ResAlloc.StartBusEnumeration = StartBusEnumeration;
- HostBridge->ResAlloc.SetBusNumbers = SetBusNumbers;
- HostBridge->ResAlloc.SubmitResources = SubmitResources;
+ HostBridge->ResAlloc.NotifyPhase = NotifyPhase;
+ HostBridge->ResAlloc.GetNextRootBridge = GetNextRootBridge;
+ HostBridge->ResAlloc.GetAllocAttributes = GetAttributes;
+ HostBridge->ResAlloc.StartBusEnumeration = StartBusEnumeration;
+ HostBridge->ResAlloc.SetBusNumbers = SetBusNumbers;
+ HostBridge->ResAlloc.SubmitResources = SubmitResources;
HostBridge->ResAlloc.GetProposedResources = GetProposedResources;
HostBridge->ResAlloc.PreprocessController = PreprocessController;
Status = gBS->InstallMultipleProtocolInterfaces (
&HostBridge->Handle,
- &gEfiPciHostBridgeResourceAllocationProtocolGuid, &HostBridge->ResAlloc,
+ &gEfiPciHostBridgeResourceAllocationProtocolGuid,
+ &HostBridge->ResAlloc,
NULL
);
ASSERT_EFI_ERROR (Status);
@@ -539,18 +604,22 @@ InitializePciHostBridge ( for (Link = GetFirstNode (&HostBridge->RootBridges)
; !IsNull (&HostBridge->RootBridges, Link)
; Link = GetNextNode (&HostBridge->RootBridges, Link)
- ) {
- RootBridge = ROOT_BRIDGE_FROM_LINK (Link);
+ )
+ {
+ RootBridge = ROOT_BRIDGE_FROM_LINK (Link);
RootBridge->RootBridgeIo.ParentHandle = HostBridge->Handle;
Status = gBS->InstallMultipleProtocolInterfaces (
&RootBridge->Handle,
- &gEfiDevicePathProtocolGuid, RootBridge->DevicePath,
- &gEfiPciRootBridgeIoProtocolGuid, &RootBridge->RootBridgeIo,
+ &gEfiDevicePathProtocolGuid,
+ RootBridge->DevicePath,
+ &gEfiPciRootBridgeIoProtocolGuid,
+ &RootBridge->RootBridgeIo,
NULL
);
ASSERT_EFI_ERROR (Status);
}
+
PciHostBridgeFreeRootBridges (RootBridges, RootBridgeCount);
if (!EFI_ERROR (Status)) {
@@ -573,23 +642,24 @@ InitializePciHostBridge ( **/
VOID
ResourceConflict (
- IN PCI_HOST_BRIDGE_INSTANCE *HostBridge
+ IN PCI_HOST_BRIDGE_INSTANCE *HostBridge
)
{
- EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Resources;
- EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Descriptor;
- EFI_ACPI_END_TAG_DESCRIPTOR *End;
- PCI_ROOT_BRIDGE_INSTANCE *RootBridge;
- LIST_ENTRY *Link;
- UINTN RootBridgeCount;
- PCI_RESOURCE_TYPE Index;
- PCI_RES_NODE *ResAllocNode;
+ EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Resources;
+ EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Descriptor;
+ EFI_ACPI_END_TAG_DESCRIPTOR *End;
+ PCI_ROOT_BRIDGE_INSTANCE *RootBridge;
+ LIST_ENTRY *Link;
+ UINTN RootBridgeCount;
+ PCI_RESOURCE_TYPE Index;
+ PCI_RES_NODE *ResAllocNode;
RootBridgeCount = 0;
for (Link = GetFirstNode (&HostBridge->RootBridges)
; !IsNull (&HostBridge->RootBridges, Link)
; Link = GetNextNode (&HostBridge->RootBridges, Link)
- ) {
+ )
+ {
RootBridgeCount++;
}
@@ -602,61 +672,63 @@ ResourceConflict ( for (Link = GetFirstNode (&HostBridge->RootBridges), Descriptor = Resources
; !IsNull (&HostBridge->RootBridges, Link)
; Link = GetNextNode (&HostBridge->RootBridges, Link)
- ) {
+ )
+ {
RootBridge = ROOT_BRIDGE_FROM_LINK (Link);
for (Index = TypeIo; Index < TypeMax; Index++) {
ResAllocNode = &RootBridge->ResAllocNode[Index];
- Descriptor->Desc = ACPI_ADDRESS_SPACE_DESCRIPTOR;
- Descriptor->Len = sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) - 3;
+ Descriptor->Desc = ACPI_ADDRESS_SPACE_DESCRIPTOR;
+ Descriptor->Len = sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) - 3;
Descriptor->AddrRangeMin = ResAllocNode->Base;
Descriptor->AddrRangeMax = ResAllocNode->Alignment;
Descriptor->AddrLen = ResAllocNode->Length;
Descriptor->SpecificFlag = 0;
switch (ResAllocNode->Type) {
+ case TypeIo:
+ Descriptor->ResType = ACPI_ADDRESS_SPACE_TYPE_IO;
+ break;
+
+ case TypePMem32:
+ Descriptor->SpecificFlag = EFI_ACPI_MEMORY_RESOURCE_SPECIFIC_FLAG_CACHEABLE_PREFETCHABLE;
+ case TypeMem32:
+ Descriptor->ResType = ACPI_ADDRESS_SPACE_TYPE_MEM;
+ Descriptor->AddrSpaceGranularity = 32;
+ break;
+
+ case TypePMem64:
+ Descriptor->SpecificFlag = EFI_ACPI_MEMORY_RESOURCE_SPECIFIC_FLAG_CACHEABLE_PREFETCHABLE;
+ case TypeMem64:
+ Descriptor->ResType = ACPI_ADDRESS_SPACE_TYPE_MEM;
+ Descriptor->AddrSpaceGranularity = 64;
+ break;
+
+ case TypeBus:
+ Descriptor->ResType = ACPI_ADDRESS_SPACE_TYPE_BUS;
+ break;
- case TypeIo:
- Descriptor->ResType = ACPI_ADDRESS_SPACE_TYPE_IO;
- break;
-
- case TypePMem32:
- Descriptor->SpecificFlag = EFI_ACPI_MEMORY_RESOURCE_SPECIFIC_FLAG_CACHEABLE_PREFETCHABLE;
- case TypeMem32:
- Descriptor->ResType = ACPI_ADDRESS_SPACE_TYPE_MEM;
- Descriptor->AddrSpaceGranularity = 32;
- break;
-
- case TypePMem64:
- Descriptor->SpecificFlag = EFI_ACPI_MEMORY_RESOURCE_SPECIFIC_FLAG_CACHEABLE_PREFETCHABLE;
- case TypeMem64:
- Descriptor->ResType = ACPI_ADDRESS_SPACE_TYPE_MEM;
- Descriptor->AddrSpaceGranularity = 64;
- break;
-
- case TypeBus:
- Descriptor->ResType = ACPI_ADDRESS_SPACE_TYPE_BUS;
- break;
-
- default:
- break;
+ default:
+ break;
}
Descriptor++;
}
+
//
// Terminate the root bridge resources.
//
- End = (EFI_ACPI_END_TAG_DESCRIPTOR *) Descriptor;
- End->Desc = ACPI_END_TAG_DESCRIPTOR;
+ End = (EFI_ACPI_END_TAG_DESCRIPTOR *)Descriptor;
+ End->Desc = ACPI_END_TAG_DESCRIPTOR;
End->Checksum = 0x0;
- Descriptor = (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *) (End + 1);
+ Descriptor = (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)(End + 1);
}
+
//
// Terminate the host bridge resources.
//
- End = (EFI_ACPI_END_TAG_DESCRIPTOR *) Descriptor;
- End->Desc = ACPI_END_TAG_DESCRIPTOR;
+ End = (EFI_ACPI_END_TAG_DESCRIPTOR *)Descriptor;
+ End->Desc = ACPI_END_TAG_DESCRIPTOR;
End->Checksum = 0x0;
DEBUG ((DEBUG_ERROR, "Call PciHostBridgeResourceConflict().\n"));
@@ -679,14 +751,14 @@ ResourceConflict ( **/
UINT64
AllocateResource (
- BOOLEAN Mmio,
- UINT64 Length,
- UINTN BitsOfAlignment,
- UINT64 BaseAddress,
- UINT64 Limit
+ BOOLEAN Mmio,
+ UINT64 Length,
+ UINTN BitsOfAlignment,
+ UINT64 BaseAddress,
+ UINT64 Limit
)
{
- EFI_STATUS Status;
+ EFI_STATUS Status;
if (BaseAddress < Limit) {
//
@@ -725,9 +797,11 @@ AllocateResource ( if (!EFI_ERROR (Status)) {
return BaseAddress;
}
+
BaseAddress += LShiftU64 (1, BitsOfAlignment);
}
}
+
return MAX_UINT64;
}
@@ -746,331 +820,374 @@ AllocateResource ( EFI_STATUS
EFIAPI
NotifyPhase (
- IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,
- IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PHASE Phase
+ IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,
+ IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PHASE Phase
)
{
- PCI_HOST_BRIDGE_INSTANCE *HostBridge;
- PCI_ROOT_BRIDGE_INSTANCE *RootBridge;
- LIST_ENTRY *Link;
- EFI_PHYSICAL_ADDRESS BaseAddress;
- UINTN BitsOfAlignment;
- UINT64 Alignment;
- EFI_STATUS Status;
- EFI_STATUS ReturnStatus;
- PCI_RESOURCE_TYPE Index;
- PCI_RESOURCE_TYPE Index1;
- PCI_RESOURCE_TYPE Index2;
- BOOLEAN ResNodeHandled[TypeMax];
- UINT64 MaxAlignment;
- UINT64 Translation;
+ PCI_HOST_BRIDGE_INSTANCE *HostBridge;
+ PCI_ROOT_BRIDGE_INSTANCE *RootBridge;
+ LIST_ENTRY *Link;
+ EFI_PHYSICAL_ADDRESS BaseAddress;
+ UINTN BitsOfAlignment;
+ UINT64 Alignment;
+ EFI_STATUS Status;
+ EFI_STATUS ReturnStatus;
+ PCI_RESOURCE_TYPE Index;
+ PCI_RESOURCE_TYPE Index1;
+ PCI_RESOURCE_TYPE Index2;
+ BOOLEAN ResNodeHandled[TypeMax];
+ UINT64 MaxAlignment;
+ UINT64 Translation;
HostBridge = PCI_HOST_BRIDGE_FROM_THIS (This);
switch (Phase) {
- case EfiPciHostBridgeBeginEnumeration:
- if (!HostBridge->CanRestarted) {
- return EFI_NOT_READY;
- }
- //
- // Reset Root Bridge
- //
- for (Link = GetFirstNode (&HostBridge->RootBridges)
- ; !IsNull (&HostBridge->RootBridges, Link)
- ; Link = GetNextNode (&HostBridge->RootBridges, Link)
- ) {
- RootBridge = ROOT_BRIDGE_FROM_LINK (Link);
- for (Index = TypeIo; Index < TypeMax; Index++) {
- RootBridge->ResAllocNode[Index].Type = Index;
- RootBridge->ResAllocNode[Index].Base = 0;
- RootBridge->ResAllocNode[Index].Length = 0;
- RootBridge->ResAllocNode[Index].Status = ResNone;
-
- RootBridge->ResourceSubmitted = FALSE;
+ case EfiPciHostBridgeBeginEnumeration:
+ if (!HostBridge->CanRestarted) {
+ return EFI_NOT_READY;
}
- }
- HostBridge->CanRestarted = TRUE;
- break;
+ //
+ // Reset Root Bridge
+ //
+ for (Link = GetFirstNode (&HostBridge->RootBridges)
+ ; !IsNull (&HostBridge->RootBridges, Link)
+ ; Link = GetNextNode (&HostBridge->RootBridges, Link)
+ )
+ {
+ RootBridge = ROOT_BRIDGE_FROM_LINK (Link);
+ for (Index = TypeIo; Index < TypeMax; Index++) {
+ RootBridge->ResAllocNode[Index].Type = Index;
+ RootBridge->ResAllocNode[Index].Base = 0;
+ RootBridge->ResAllocNode[Index].Length = 0;
+ RootBridge->ResAllocNode[Index].Status = ResNone;
+
+ RootBridge->ResourceSubmitted = FALSE;
+ }
+ }
- case EfiPciHostBridgeBeginBusAllocation:
- //
- // No specific action is required here, can perform any chipset specific programing
- //
- HostBridge->CanRestarted = FALSE;
- break;
+ HostBridge->CanRestarted = TRUE;
+ break;
- case EfiPciHostBridgeEndBusAllocation:
- //
- // No specific action is required here, can perform any chipset specific programing
- //
- break;
+ case EfiPciHostBridgeBeginBusAllocation:
+ //
+ // No specific action is required here, can perform any chipset specific programing
+ //
+ HostBridge->CanRestarted = FALSE;
+ break;
- case EfiPciHostBridgeBeginResourceAllocation:
- //
- // No specific action is required here, can perform any chipset specific programing
- //
- break;
+ case EfiPciHostBridgeEndBusAllocation:
+ //
+ // No specific action is required here, can perform any chipset specific programing
+ //
+ break;
- case EfiPciHostBridgeAllocateResources:
- ReturnStatus = EFI_SUCCESS;
+ case EfiPciHostBridgeBeginResourceAllocation:
+ //
+ // No specific action is required here, can perform any chipset specific programing
+ //
+ break;
- //
- // Make sure the resource for all root bridges has been submitted.
- //
- for (Link = GetFirstNode (&HostBridge->RootBridges)
- ; !IsNull (&HostBridge->RootBridges, Link)
- ; Link = GetNextNode (&HostBridge->RootBridges, Link)
- ) {
- RootBridge = ROOT_BRIDGE_FROM_LINK (Link);
- if (!RootBridge->ResourceSubmitted) {
- return EFI_NOT_READY;
- }
- }
+ case EfiPciHostBridgeAllocateResources:
+ ReturnStatus = EFI_SUCCESS;
- DEBUG ((DEBUG_INFO, "PciHostBridge: NotifyPhase (AllocateResources)\n"));
- for (Link = GetFirstNode (&HostBridge->RootBridges)
- ; !IsNull (&HostBridge->RootBridges, Link)
- ; Link = GetNextNode (&HostBridge->RootBridges, Link)
- ) {
- for (Index = TypeIo; Index < TypeBus; Index++) {
- ResNodeHandled[Index] = FALSE;
+ //
+ // Make sure the resource for all root bridges has been submitted.
+ //
+ for (Link = GetFirstNode (&HostBridge->RootBridges)
+ ; !IsNull (&HostBridge->RootBridges, Link)
+ ; Link = GetNextNode (&HostBridge->RootBridges, Link)
+ )
+ {
+ RootBridge = ROOT_BRIDGE_FROM_LINK (Link);
+ if (!RootBridge->ResourceSubmitted) {
+ return EFI_NOT_READY;
+ }
}
- RootBridge = ROOT_BRIDGE_FROM_LINK (Link);
- DEBUG ((DEBUG_INFO, " RootBridge: %s\n", RootBridge->DevicePathStr));
-
- for (Index1 = TypeIo; Index1 < TypeBus; Index1++) {
- if (RootBridge->ResAllocNode[Index1].Status == ResNone) {
- ResNodeHandled[Index1] = TRUE;
- } else {
- //
- // Allocate the resource node with max alignment at first
- //
- MaxAlignment = 0;
- Index = TypeMax;
- for (Index2 = TypeIo; Index2 < TypeBus; Index2++) {
- if (ResNodeHandled[Index2]) {
- continue;
- }
- if (MaxAlignment <= RootBridge->ResAllocNode[Index2].Alignment) {
- MaxAlignment = RootBridge->ResAllocNode[Index2].Alignment;
- Index = Index2;
- }
- }
+ DEBUG ((DEBUG_INFO, "PciHostBridge: NotifyPhase (AllocateResources)\n"));
+ for (Link = GetFirstNode (&HostBridge->RootBridges)
+ ; !IsNull (&HostBridge->RootBridges, Link)
+ ; Link = GetNextNode (&HostBridge->RootBridges, Link)
+ )
+ {
+ for (Index = TypeIo; Index < TypeBus; Index++) {
+ ResNodeHandled[Index] = FALSE;
+ }
- ASSERT (Index < TypeMax);
- ResNodeHandled[Index] = TRUE;
- Alignment = RootBridge->ResAllocNode[Index].Alignment;
- BitsOfAlignment = LowBitSet64 (Alignment + 1);
- BaseAddress = MAX_UINT64;
+ RootBridge = ROOT_BRIDGE_FROM_LINK (Link);
+ DEBUG ((DEBUG_INFO, " RootBridge: %s\n", RootBridge->DevicePathStr));
- //
- // RESTRICTION: To simplify the situation, we require the alignment of
- // Translation must be larger than any BAR alignment in the same root
- // bridge, so that resource allocation alignment can be applied to
- // both device address and host address.
- //
- Translation = GetTranslationByResourceType (RootBridge, Index);
- if ((Translation & Alignment) != 0) {
- DEBUG ((DEBUG_ERROR, "[%a:%d] Translation %lx is not aligned to %lx!\n",
- __FUNCTION__, DEBUG_LINE_NUMBER, Translation, Alignment
- ));
- ASSERT ((Translation & Alignment) == 0);
+ for (Index1 = TypeIo; Index1 < TypeBus; Index1++) {
+ if (RootBridge->ResAllocNode[Index1].Status == ResNone) {
+ ResNodeHandled[Index1] = TRUE;
+ } else {
//
- // This may be caused by too large alignment or too small
- // Translation; pick the 1st possibility and return out of resource,
- // which can also go thru the same process for out of resource
- // outside the loop.
+ // Allocate the resource node with max alignment at first
//
- ReturnStatus = EFI_OUT_OF_RESOURCES;
- continue;
- }
+ MaxAlignment = 0;
+ Index = TypeMax;
+ for (Index2 = TypeIo; Index2 < TypeBus; Index2++) {
+ if (ResNodeHandled[Index2]) {
+ continue;
+ }
+
+ if (MaxAlignment <= RootBridge->ResAllocNode[Index2].Alignment) {
+ MaxAlignment = RootBridge->ResAllocNode[Index2].Alignment;
+ Index = Index2;
+ }
+ }
- switch (Index) {
- case TypeIo:
- //
- // Base and Limit in PCI_ROOT_BRIDGE_APERTURE are device address.
- // For AllocateResource is manipulating GCD resource, we need to use
- // host address here.
- //
- BaseAddress = AllocateResource (
- FALSE,
- RootBridge->ResAllocNode[Index].Length,
- MIN (15, BitsOfAlignment),
- TO_HOST_ADDRESS (ALIGN_VALUE (RootBridge->Io.Base, Alignment + 1),
- RootBridge->Io.Translation),
- TO_HOST_ADDRESS (RootBridge->Io.Limit,
- RootBridge->Io.Translation)
- );
- break;
+ ASSERT (Index < TypeMax);
+ ResNodeHandled[Index] = TRUE;
+ Alignment = RootBridge->ResAllocNode[Index].Alignment;
+ BitsOfAlignment = LowBitSet64 (Alignment + 1);
+ BaseAddress = MAX_UINT64;
- case TypeMem64:
- BaseAddress = AllocateResource (
- TRUE,
- RootBridge->ResAllocNode[Index].Length,
- MIN (63, BitsOfAlignment),
- TO_HOST_ADDRESS (ALIGN_VALUE (RootBridge->MemAbove4G.Base, Alignment + 1),
- RootBridge->MemAbove4G.Translation),
- TO_HOST_ADDRESS (RootBridge->MemAbove4G.Limit,
- RootBridge->MemAbove4G.Translation)
- );
- if (BaseAddress != MAX_UINT64) {
- break;
- }
//
- // If memory above 4GB is not available, try memory below 4GB
+ // RESTRICTION: To simplify the situation, we require the alignment of
+ // Translation must be larger than any BAR alignment in the same root
+ // bridge, so that resource allocation alignment can be applied to
+ // both device address and host address.
//
+ Translation = GetTranslationByResourceType (RootBridge, Index);
+ if ((Translation & Alignment) != 0) {
+ DEBUG ((
+ DEBUG_ERROR,
+ "[%a:%d] Translation %lx is not aligned to %lx!\n",
+ __FUNCTION__,
+ DEBUG_LINE_NUMBER,
+ Translation,
+ Alignment
+ ));
+ ASSERT ((Translation & Alignment) == 0);
+ //
+ // This may be caused by too large alignment or too small
+ // Translation; pick the 1st possibility and return out of resource,
+ // which can also go thru the same process for out of resource
+ // outside the loop.
+ //
+ ReturnStatus = EFI_OUT_OF_RESOURCES;
+ continue;
+ }
- case TypeMem32:
- BaseAddress = AllocateResource (
- TRUE,
- RootBridge->ResAllocNode[Index].Length,
- MIN (31, BitsOfAlignment),
- TO_HOST_ADDRESS (ALIGN_VALUE (RootBridge->Mem.Base, Alignment + 1),
- RootBridge->Mem.Translation),
- TO_HOST_ADDRESS (RootBridge->Mem.Limit,
- RootBridge->Mem.Translation)
- );
- break;
+ switch (Index) {
+ case TypeIo:
+ //
+ // Base and Limit in PCI_ROOT_BRIDGE_APERTURE are device address.
+ // For AllocateResource is manipulating GCD resource, we need to use
+ // host address here.
+ //
+ BaseAddress = AllocateResource (
+ FALSE,
+ RootBridge->ResAllocNode[Index].Length,
+ MIN (15, BitsOfAlignment),
+ TO_HOST_ADDRESS (
+ ALIGN_VALUE (RootBridge->Io.Base, Alignment + 1),
+ RootBridge->Io.Translation
+ ),
+ TO_HOST_ADDRESS (
+ RootBridge->Io.Limit,
+ RootBridge->Io.Translation
+ )
+ );
+ break;
+
+ case TypeMem64:
+ BaseAddress = AllocateResource (
+ TRUE,
+ RootBridge->ResAllocNode[Index].Length,
+ MIN (63, BitsOfAlignment),
+ TO_HOST_ADDRESS (
+ ALIGN_VALUE (RootBridge->MemAbove4G.Base, Alignment + 1),
+ RootBridge->MemAbove4G.Translation
+ ),
+ TO_HOST_ADDRESS (
+ RootBridge->MemAbove4G.Limit,
+ RootBridge->MemAbove4G.Translation
+ )
+ );
+ if (BaseAddress != MAX_UINT64) {
+ break;
+ }
+
+ //
+ // If memory above 4GB is not available, try memory below 4GB
+ //
+
+ case TypeMem32:
+ BaseAddress = AllocateResource (
+ TRUE,
+ RootBridge->ResAllocNode[Index].Length,
+ MIN (31, BitsOfAlignment),
+ TO_HOST_ADDRESS (
+ ALIGN_VALUE (RootBridge->Mem.Base, Alignment + 1),
+ RootBridge->Mem.Translation
+ ),
+ TO_HOST_ADDRESS (
+ RootBridge->Mem.Limit,
+ RootBridge->Mem.Translation
+ )
+ );
+ break;
+
+ case TypePMem64:
+ BaseAddress = AllocateResource (
+ TRUE,
+ RootBridge->ResAllocNode[Index].Length,
+ MIN (63, BitsOfAlignment),
+ TO_HOST_ADDRESS (
+ ALIGN_VALUE (RootBridge->PMemAbove4G.Base, Alignment + 1),
+ RootBridge->PMemAbove4G.Translation
+ ),
+ TO_HOST_ADDRESS (
+ RootBridge->PMemAbove4G.Limit,
+ RootBridge->PMemAbove4G.Translation
+ )
+ );
+ if (BaseAddress != MAX_UINT64) {
+ break;
+ }
+
+ //
+ // If memory above 4GB is not available, try memory below 4GB
+ //
+ case TypePMem32:
+ BaseAddress = AllocateResource (
+ TRUE,
+ RootBridge->ResAllocNode[Index].Length,
+ MIN (31, BitsOfAlignment),
+ TO_HOST_ADDRESS (
+ ALIGN_VALUE (RootBridge->PMem.Base, Alignment + 1),
+ RootBridge->PMem.Translation
+ ),
+ TO_HOST_ADDRESS (
+ RootBridge->PMem.Limit,
+ RootBridge->PMem.Translation
+ )
+ );
+ break;
+
+ default:
+ ASSERT (FALSE);
+ break;
+ }
- case TypePMem64:
- BaseAddress = AllocateResource (
- TRUE,
- RootBridge->ResAllocNode[Index].Length,
- MIN (63, BitsOfAlignment),
- TO_HOST_ADDRESS (ALIGN_VALUE (RootBridge->PMemAbove4G.Base, Alignment + 1),
- RootBridge->PMemAbove4G.Translation),
- TO_HOST_ADDRESS (RootBridge->PMemAbove4G.Limit,
- RootBridge->PMemAbove4G.Translation)
- );
+ DEBUG ((
+ DEBUG_INFO,
+ " %s: Base/Length/Alignment = %lx/%lx/%lx - ",
+ mPciResourceTypeStr[Index],
+ BaseAddress,
+ RootBridge->ResAllocNode[Index].Length,
+ Alignment
+ ));
if (BaseAddress != MAX_UINT64) {
- break;
+ RootBridge->ResAllocNode[Index].Base = BaseAddress;
+ RootBridge->ResAllocNode[Index].Status = ResAllocated;
+ DEBUG ((DEBUG_INFO, "Success\n"));
+ } else {
+ ReturnStatus = EFI_OUT_OF_RESOURCES;
+ DEBUG ((DEBUG_ERROR, "Out Of Resource!\n"));
}
- //
- // If memory above 4GB is not available, try memory below 4GB
- //
- case TypePMem32:
- BaseAddress = AllocateResource (
- TRUE,
- RootBridge->ResAllocNode[Index].Length,
- MIN (31, BitsOfAlignment),
- TO_HOST_ADDRESS (ALIGN_VALUE (RootBridge->PMem.Base, Alignment + 1),
- RootBridge->PMem.Translation),
- TO_HOST_ADDRESS (RootBridge->PMem.Limit,
- RootBridge->PMem.Translation)
- );
- break;
-
- default:
- ASSERT (FALSE);
- break;
- }
-
- DEBUG ((DEBUG_INFO, " %s: Base/Length/Alignment = %lx/%lx/%lx - ",
- mPciResourceTypeStr[Index], BaseAddress, RootBridge->ResAllocNode[Index].Length, Alignment));
- if (BaseAddress != MAX_UINT64) {
- RootBridge->ResAllocNode[Index].Base = BaseAddress;
- RootBridge->ResAllocNode[Index].Status = ResAllocated;
- DEBUG ((DEBUG_INFO, "Success\n"));
- } else {
- ReturnStatus = EFI_OUT_OF_RESOURCES;
- DEBUG ((DEBUG_ERROR, "Out Of Resource!\n"));
}
}
}
- }
- if (ReturnStatus == EFI_OUT_OF_RESOURCES) {
- ResourceConflict (HostBridge);
- }
+ if (ReturnStatus == EFI_OUT_OF_RESOURCES) {
+ ResourceConflict (HostBridge);
+ }
- //
- // Set resource to zero for nodes where allocation fails
- //
- for (Link = GetFirstNode (&HostBridge->RootBridges)
- ; !IsNull (&HostBridge->RootBridges, Link)
- ; Link = GetNextNode (&HostBridge->RootBridges, Link)
- ) {
- RootBridge = ROOT_BRIDGE_FROM_LINK (Link);
- for (Index = TypeIo; Index < TypeBus; Index++) {
- if (RootBridge->ResAllocNode[Index].Status != ResAllocated) {
- RootBridge->ResAllocNode[Index].Length = 0;
+ //
+ // Set resource to zero for nodes where allocation fails
+ //
+ for (Link = GetFirstNode (&HostBridge->RootBridges)
+ ; !IsNull (&HostBridge->RootBridges, Link)
+ ; Link = GetNextNode (&HostBridge->RootBridges, Link)
+ )
+ {
+ RootBridge = ROOT_BRIDGE_FROM_LINK (Link);
+ for (Index = TypeIo; Index < TypeBus; Index++) {
+ if (RootBridge->ResAllocNode[Index].Status != ResAllocated) {
+ RootBridge->ResAllocNode[Index].Length = 0;
+ }
}
}
- }
- return ReturnStatus;
- case EfiPciHostBridgeSetResources:
- //
- // HostBridgeInstance->CanRestarted = FALSE;
- //
- break;
+ return ReturnStatus;
- case EfiPciHostBridgeFreeResources:
- //
- // HostBridgeInstance->CanRestarted = FALSE;
- //
- ReturnStatus = EFI_SUCCESS;
- for (Link = GetFirstNode (&HostBridge->RootBridges)
- ; !IsNull (&HostBridge->RootBridges, Link)
- ; Link = GetNextNode (&HostBridge->RootBridges, Link)
- ) {
- RootBridge = ROOT_BRIDGE_FROM_LINK (Link);
- for (Index = TypeIo; Index < TypeBus; Index++) {
- if (RootBridge->ResAllocNode[Index].Status == ResAllocated) {
- switch (Index) {
- case TypeIo:
- Status = gDS->FreeIoSpace (RootBridge->ResAllocNode[Index].Base, RootBridge->ResAllocNode[Index].Length);
- if (EFI_ERROR (Status)) {
- ReturnStatus = Status;
- }
- break;
+ case EfiPciHostBridgeSetResources:
+ //
+ // HostBridgeInstance->CanRestarted = FALSE;
+ //
+ break;
- case TypeMem32:
- case TypePMem32:
- case TypeMem64:
- case TypePMem64:
- Status = gDS->FreeMemorySpace (RootBridge->ResAllocNode[Index].Base, RootBridge->ResAllocNode[Index].Length);
- if (EFI_ERROR (Status)) {
- ReturnStatus = Status;
+ case EfiPciHostBridgeFreeResources:
+ //
+ // HostBridgeInstance->CanRestarted = FALSE;
+ //
+ ReturnStatus = EFI_SUCCESS;
+ for (Link = GetFirstNode (&HostBridge->RootBridges)
+ ; !IsNull (&HostBridge->RootBridges, Link)
+ ; Link = GetNextNode (&HostBridge->RootBridges, Link)
+ )
+ {
+ RootBridge = ROOT_BRIDGE_FROM_LINK (Link);
+ for (Index = TypeIo; Index < TypeBus; Index++) {
+ if (RootBridge->ResAllocNode[Index].Status == ResAllocated) {
+ switch (Index) {
+ case TypeIo:
+ Status = gDS->FreeIoSpace (RootBridge->ResAllocNode[Index].Base, RootBridge->ResAllocNode[Index].Length);
+ if (EFI_ERROR (Status)) {
+ ReturnStatus = Status;
+ }
+
+ break;
+
+ case TypeMem32:
+ case TypePMem32:
+ case TypeMem64:
+ case TypePMem64:
+ Status = gDS->FreeMemorySpace (RootBridge->ResAllocNode[Index].Base, RootBridge->ResAllocNode[Index].Length);
+ if (EFI_ERROR (Status)) {
+ ReturnStatus = Status;
+ }
+
+ break;
+
+ default:
+ ASSERT (FALSE);
+ break;
}
- break;
- default:
- ASSERT (FALSE);
- break;
+ RootBridge->ResAllocNode[Index].Type = Index;
+ RootBridge->ResAllocNode[Index].Base = 0;
+ RootBridge->ResAllocNode[Index].Length = 0;
+ RootBridge->ResAllocNode[Index].Status = ResNone;
}
-
- RootBridge->ResAllocNode[Index].Type = Index;
- RootBridge->ResAllocNode[Index].Base = 0;
- RootBridge->ResAllocNode[Index].Length = 0;
- RootBridge->ResAllocNode[Index].Status = ResNone;
}
- }
- RootBridge->ResourceSubmitted = FALSE;
- }
+ RootBridge->ResourceSubmitted = FALSE;
+ }
- HostBridge->CanRestarted = TRUE;
- return ReturnStatus;
+ HostBridge->CanRestarted = TRUE;
+ return ReturnStatus;
- case EfiPciHostBridgeEndResourceAllocation:
- //
- // The resource allocation phase is completed. No specific action is required
- // here. This notification can be used to perform any chipset specific programming.
- //
- break;
+ case EfiPciHostBridgeEndResourceAllocation:
+ //
+ // The resource allocation phase is completed. No specific action is required
+ // here. This notification can be used to perform any chipset specific programming.
+ //
+ break;
- case EfiPciHostBridgeEndEnumeration:
- //
- // The Host Bridge Enumeration is completed. No specific action is required here.
- // This notification can be used to perform any chipset specific programming.
- //
- break;
+ case EfiPciHostBridgeEndEnumeration:
+ //
+ // The Host Bridge Enumeration is completed. No specific action is required here.
+ // This notification can be used to perform any chipset specific programming.
+ //
+ break;
- default:
- return EFI_INVALID_PARAMETER;
+ default:
+ return EFI_INVALID_PARAMETER;
}
return EFI_SUCCESS;
@@ -1095,8 +1212,8 @@ NotifyPhase ( EFI_STATUS
EFIAPI
GetNextRootBridge (
- IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,
- IN OUT EFI_HANDLE *RootBridgeHandle
+ IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,
+ IN OUT EFI_HANDLE *RootBridgeHandle
)
{
BOOLEAN ReturnNext;
@@ -1109,19 +1226,20 @@ GetNextRootBridge ( }
HostBridge = PCI_HOST_BRIDGE_FROM_THIS (This);
- ReturnNext = (BOOLEAN) (*RootBridgeHandle == NULL);
+ ReturnNext = (BOOLEAN)(*RootBridgeHandle == NULL);
for (Link = GetFirstNode (&HostBridge->RootBridges)
- ; !IsNull (&HostBridge->RootBridges, Link)
- ; Link = GetNextNode (&HostBridge->RootBridges, Link)
- ) {
+ ; !IsNull (&HostBridge->RootBridges, Link)
+ ; Link = GetNextNode (&HostBridge->RootBridges, Link)
+ )
+ {
RootBridge = ROOT_BRIDGE_FROM_LINK (Link);
if (ReturnNext) {
*RootBridgeHandle = RootBridge->Handle;
return EFI_SUCCESS;
}
- ReturnNext = (BOOLEAN) (*RootBridgeHandle == RootBridge->Handle);
+ ReturnNext = (BOOLEAN)(*RootBridgeHandle == RootBridge->Handle);
}
if (ReturnNext) {
@@ -1151,9 +1269,9 @@ GetNextRootBridge ( EFI_STATUS
EFIAPI
GetAttributes (
- IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,
- IN EFI_HANDLE RootBridgeHandle,
- OUT UINT64 *Attributes
+ IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,
+ IN EFI_HANDLE RootBridgeHandle,
+ OUT UINT64 *Attributes
)
{
LIST_ENTRY *Link;
@@ -1166,9 +1284,10 @@ GetAttributes ( HostBridge = PCI_HOST_BRIDGE_FROM_THIS (This);
for (Link = GetFirstNode (&HostBridge->RootBridges)
- ; !IsNull (&HostBridge->RootBridges, Link)
- ; Link = GetNextNode (&HostBridge->RootBridges, Link)
- ) {
+ ; !IsNull (&HostBridge->RootBridges, Link)
+ ; Link = GetNextNode (&HostBridge->RootBridges, Link)
+ )
+ {
RootBridge = ROOT_BRIDGE_FROM_LINK (Link);
if (RootBridgeHandle == RootBridge->Handle) {
*Attributes = RootBridge->AllocationAttributes;
@@ -1196,16 +1315,16 @@ GetAttributes ( EFI_STATUS
EFIAPI
StartBusEnumeration (
- IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,
- IN EFI_HANDLE RootBridgeHandle,
- OUT VOID **Configuration
+ IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,
+ IN EFI_HANDLE RootBridgeHandle,
+ OUT VOID **Configuration
)
{
- LIST_ENTRY *Link;
- PCI_HOST_BRIDGE_INSTANCE *HostBridge;
- PCI_ROOT_BRIDGE_INSTANCE *RootBridge;
- EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Descriptor;
- EFI_ACPI_END_TAG_DESCRIPTOR *End;
+ LIST_ENTRY *Link;
+ PCI_HOST_BRIDGE_INSTANCE *HostBridge;
+ PCI_ROOT_BRIDGE_INSTANCE *RootBridge;
+ EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Descriptor;
+ EFI_ACPI_END_TAG_DESCRIPTOR *End;
if (Configuration == NULL) {
return EFI_INVALID_PARAMETER;
@@ -1215,7 +1334,8 @@ StartBusEnumeration ( for (Link = GetFirstNode (&HostBridge->RootBridges)
; !IsNull (&HostBridge->RootBridges, Link)
; Link = GetNextNode (&HostBridge->RootBridges, Link)
- ) {
+ )
+ {
RootBridge = ROOT_BRIDGE_FROM_LINK (Link);
if (RootBridgeHandle == RootBridge->Handle) {
*Configuration = AllocatePool (sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) + sizeof (EFI_ACPI_END_TAG_DESCRIPTOR));
@@ -1223,7 +1343,7 @@ StartBusEnumeration ( return EFI_OUT_OF_RESOURCES;
}
- Descriptor = (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *) *Configuration;
+ Descriptor = (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)*Configuration;
Descriptor->Desc = ACPI_ADDRESS_SPACE_DESCRIPTOR;
Descriptor->Len = sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) - 3;
Descriptor->ResType = ACPI_ADDRESS_SPACE_TYPE_BUS;
@@ -1235,8 +1355,8 @@ StartBusEnumeration ( Descriptor->AddrTranslationOffset = 0;
Descriptor->AddrLen = RootBridge->Bus.Limit - RootBridge->Bus.Base + 1;
- End = (EFI_ACPI_END_TAG_DESCRIPTOR *) (Descriptor + 1);
- End->Desc = ACPI_END_TAG_DESCRIPTOR;
+ End = (EFI_ACPI_END_TAG_DESCRIPTOR *)(Descriptor + 1);
+ End->Desc = ACPI_END_TAG_DESCRIPTOR;
End->Checksum = 0x0;
return EFI_SUCCESS;
@@ -1262,23 +1382,23 @@ StartBusEnumeration ( EFI_STATUS
EFIAPI
SetBusNumbers (
- IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,
- IN EFI_HANDLE RootBridgeHandle,
- IN VOID *Configuration
+ IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,
+ IN EFI_HANDLE RootBridgeHandle,
+ IN VOID *Configuration
)
{
- LIST_ENTRY *Link;
- PCI_HOST_BRIDGE_INSTANCE *HostBridge;
- PCI_ROOT_BRIDGE_INSTANCE *RootBridge;
- EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Descriptor;
- EFI_ACPI_END_TAG_DESCRIPTOR *End;
+ LIST_ENTRY *Link;
+ PCI_HOST_BRIDGE_INSTANCE *HostBridge;
+ PCI_ROOT_BRIDGE_INSTANCE *RootBridge;
+ EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Descriptor;
+ EFI_ACPI_END_TAG_DESCRIPTOR *End;
if (Configuration == NULL) {
return EFI_INVALID_PARAMETER;
}
- Descriptor = (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *) Configuration;
- End = (EFI_ACPI_END_TAG_DESCRIPTOR *) (Descriptor + 1);
+ Descriptor = (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)Configuration;
+ End = (EFI_ACPI_END_TAG_DESCRIPTOR *)(Descriptor + 1);
//
// Check the Configuration is valid
@@ -1286,7 +1406,8 @@ SetBusNumbers ( if ((Descriptor->Desc != ACPI_ADDRESS_SPACE_DESCRIPTOR) ||
(Descriptor->ResType != ACPI_ADDRESS_SPACE_TYPE_BUS) ||
(End->Desc != ACPI_END_TAG_DESCRIPTOR)
- ) {
+ )
+ {
return EFI_INVALID_PARAMETER;
}
@@ -1294,25 +1415,27 @@ SetBusNumbers ( for (Link = GetFirstNode (&HostBridge->RootBridges)
; !IsNull (&HostBridge->RootBridges, Link)
; Link = GetNextNode (&HostBridge->RootBridges, Link)
- ) {
+ )
+ {
RootBridge = ROOT_BRIDGE_FROM_LINK (Link);
if (RootBridgeHandle == RootBridge->Handle) {
-
if (Descriptor->AddrLen == 0) {
return EFI_INVALID_PARAMETER;
}
if ((Descriptor->AddrRangeMin < RootBridge->Bus.Base) ||
(Descriptor->AddrRangeMin + Descriptor->AddrLen - 1 > RootBridge->Bus.Limit)
- ) {
+ )
+ {
return EFI_INVALID_PARAMETER;
}
+
//
// Update the Bus Range
//
- RootBridge->ResAllocNode[TypeBus].Base = Descriptor->AddrRangeMin;
- RootBridge->ResAllocNode[TypeBus].Length = Descriptor->AddrLen;
- RootBridge->ResAllocNode[TypeBus].Status = ResAllocated;
+ RootBridge->ResAllocNode[TypeBus].Base = Descriptor->AddrRangeMin;
+ RootBridge->ResAllocNode[TypeBus].Length = Descriptor->AddrLen;
+ RootBridge->ResAllocNode[TypeBus].Status = ResAllocated;
return EFI_SUCCESS;
}
}
@@ -1335,16 +1458,16 @@ SetBusNumbers ( EFI_STATUS
EFIAPI
SubmitResources (
- IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,
- IN EFI_HANDLE RootBridgeHandle,
- IN VOID *Configuration
+ IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,
+ IN EFI_HANDLE RootBridgeHandle,
+ IN VOID *Configuration
)
{
- LIST_ENTRY *Link;
- PCI_HOST_BRIDGE_INSTANCE *HostBridge;
- PCI_ROOT_BRIDGE_INSTANCE *RootBridge;
- EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Descriptor;
- PCI_RESOURCE_TYPE Type;
+ LIST_ENTRY *Link;
+ PCI_HOST_BRIDGE_INSTANCE *HostBridge;
+ PCI_ROOT_BRIDGE_INSTANCE *RootBridge;
+ EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Descriptor;
+ PCI_RESOURCE_TYPE Type;
//
// Check the input parameter: Configuration
@@ -1357,7 +1480,8 @@ SubmitResources ( for (Link = GetFirstNode (&HostBridge->RootBridges)
; !IsNull (&HostBridge->RootBridges, Link)
; Link = GetNextNode (&HostBridge->RootBridges, Link)
- ) {
+ )
+ {
RootBridge = ROOT_BRIDGE_FROM_LINK (Link);
if (RootBridgeHandle == RootBridge->Handle) {
DEBUG ((DEBUG_INFO, "PciHostBridge: SubmitResources for %s\n", RootBridge->DevicePathStr));
@@ -1366,52 +1490,62 @@ SubmitResources ( // If the Configuration includes one or more invalid resource descriptors, all the resource
// descriptors are ignored and the function returns EFI_INVALID_PARAMETER.
//
- for (Descriptor = (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *) Configuration; Descriptor->Desc == ACPI_ADDRESS_SPACE_DESCRIPTOR; Descriptor++) {
+ for (Descriptor = (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)Configuration; Descriptor->Desc == ACPI_ADDRESS_SPACE_DESCRIPTOR; Descriptor++) {
if (Descriptor->ResType > ACPI_ADDRESS_SPACE_TYPE_BUS) {
return EFI_INVALID_PARAMETER;
}
- DEBUG ((DEBUG_INFO, " %s: Granularity/SpecificFlag = %ld / %02x%s\n",
- mAcpiAddressSpaceTypeStr[Descriptor->ResType], Descriptor->AddrSpaceGranularity, Descriptor->SpecificFlag,
- (Descriptor->SpecificFlag & EFI_ACPI_MEMORY_RESOURCE_SPECIFIC_FLAG_CACHEABLE_PREFETCHABLE) != 0 ? L" (Prefetchable)" : L""
- ));
+ DEBUG ((
+ DEBUG_INFO,
+ " %s: Granularity/SpecificFlag = %ld / %02x%s\n",
+ mAcpiAddressSpaceTypeStr[Descriptor->ResType],
+ Descriptor->AddrSpaceGranularity,
+ Descriptor->SpecificFlag,
+ (Descriptor->SpecificFlag & EFI_ACPI_MEMORY_RESOURCE_SPECIFIC_FLAG_CACHEABLE_PREFETCHABLE) != 0 ? L" (Prefetchable)" : L""
+ ));
DEBUG ((DEBUG_INFO, " Length/Alignment = 0x%lx / 0x%lx\n", Descriptor->AddrLen, Descriptor->AddrRangeMax));
switch (Descriptor->ResType) {
- case ACPI_ADDRESS_SPACE_TYPE_MEM:
- if (Descriptor->AddrSpaceGranularity != 32 && Descriptor->AddrSpaceGranularity != 64) {
- return EFI_INVALID_PARAMETER;
- }
- if (Descriptor->AddrSpaceGranularity == 32 && Descriptor->AddrLen >= SIZE_4GB) {
- return EFI_INVALID_PARAMETER;
- }
- //
- // If the PCI root bridge does not support separate windows for nonprefetchable and
- // prefetchable memory, then the PCI bus driver needs to include requests for
- // prefetchable memory in the nonprefetchable memory pool.
- //
- if (((RootBridge->AllocationAttributes & EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM) != 0) &&
- ((Descriptor->SpecificFlag & EFI_ACPI_MEMORY_RESOURCE_SPECIFIC_FLAG_CACHEABLE_PREFETCHABLE) != 0)
- ) {
- return EFI_INVALID_PARAMETER;
- }
- case ACPI_ADDRESS_SPACE_TYPE_IO:
- //
- // Check aligment, it should be of the form 2^n-1
- //
- if (GetPowerOfTwo64 (Descriptor->AddrRangeMax + 1) != (Descriptor->AddrRangeMax + 1)) {
- return EFI_INVALID_PARAMETER;
- }
- break;
- default:
- ASSERT (FALSE);
- break;
+ case ACPI_ADDRESS_SPACE_TYPE_MEM:
+ if ((Descriptor->AddrSpaceGranularity != 32) && (Descriptor->AddrSpaceGranularity != 64)) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ if ((Descriptor->AddrSpaceGranularity == 32) && (Descriptor->AddrLen >= SIZE_4GB)) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ //
+ // If the PCI root bridge does not support separate windows for nonprefetchable and
+ // prefetchable memory, then the PCI bus driver needs to include requests for
+ // prefetchable memory in the nonprefetchable memory pool.
+ //
+ if (((RootBridge->AllocationAttributes & EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM) != 0) &&
+ ((Descriptor->SpecificFlag & EFI_ACPI_MEMORY_RESOURCE_SPECIFIC_FLAG_CACHEABLE_PREFETCHABLE) != 0)
+ )
+ {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ case ACPI_ADDRESS_SPACE_TYPE_IO:
+ //
+ // Check aligment, it should be of the form 2^n-1
+ //
+ if (GetPowerOfTwo64 (Descriptor->AddrRangeMax + 1) != (Descriptor->AddrRangeMax + 1)) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ break;
+ default:
+ ASSERT (FALSE);
+ break;
}
}
+
if (Descriptor->Desc != ACPI_END_TAG_DESCRIPTOR) {
return EFI_INVALID_PARAMETER;
}
- for (Descriptor = (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *) Configuration; Descriptor->Desc == ACPI_ADDRESS_SPACE_DESCRIPTOR; Descriptor++) {
+ for (Descriptor = (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)Configuration; Descriptor->Desc == ACPI_ADDRESS_SPACE_DESCRIPTOR; Descriptor++) {
if (Descriptor->ResType == ACPI_ADDRESS_SPACE_TYPE_MEM) {
if (Descriptor->AddrSpaceGranularity == 32) {
if ((Descriptor->SpecificFlag & EFI_ACPI_MEMORY_RESOURCE_SPECIFIC_FLAG_CACHEABLE_PREFETCHABLE) != 0) {
@@ -1431,10 +1565,12 @@ SubmitResources ( ASSERT (Descriptor->ResType == ACPI_ADDRESS_SPACE_TYPE_IO);
Type = TypeIo;
}
+
RootBridge->ResAllocNode[Type].Length = Descriptor->AddrLen;
RootBridge->ResAllocNode[Type].Alignment = Descriptor->AddrRangeMax;
RootBridge->ResAllocNode[Type].Status = ResSubmitted;
}
+
RootBridge->ResourceSubmitted = TRUE;
return EFI_SUCCESS;
}
@@ -1461,26 +1597,27 @@ SubmitResources ( EFI_STATUS
EFIAPI
GetProposedResources (
- IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,
- IN EFI_HANDLE RootBridgeHandle,
- OUT VOID **Configuration
+ IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,
+ IN EFI_HANDLE RootBridgeHandle,
+ OUT VOID **Configuration
)
{
- LIST_ENTRY *Link;
- PCI_HOST_BRIDGE_INSTANCE *HostBridge;
- PCI_ROOT_BRIDGE_INSTANCE *RootBridge;
- UINTN Index;
- UINTN Number;
- VOID *Buffer;
- EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Descriptor;
- EFI_ACPI_END_TAG_DESCRIPTOR *End;
- UINT64 ResStatus;
+ LIST_ENTRY *Link;
+ PCI_HOST_BRIDGE_INSTANCE *HostBridge;
+ PCI_ROOT_BRIDGE_INSTANCE *RootBridge;
+ UINTN Index;
+ UINTN Number;
+ VOID *Buffer;
+ EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Descriptor;
+ EFI_ACPI_END_TAG_DESCRIPTOR *End;
+ UINT64 ResStatus;
HostBridge = PCI_HOST_BRIDGE_FROM_THIS (This);
for (Link = GetFirstNode (&HostBridge->RootBridges)
- ; !IsNull (&HostBridge->RootBridges, Link)
- ; Link = GetNextNode (&HostBridge->RootBridges, Link)
- ) {
+ ; !IsNull (&HostBridge->RootBridges, Link)
+ ; Link = GetNextNode (&HostBridge->RootBridges, Link)
+ )
+ {
RootBridge = ROOT_BRIDGE_FROM_LINK (Link);
if (RootBridgeHandle == RootBridge->Handle) {
for (Index = 0, Number = 0; Index < TypeBus; Index++) {
@@ -1494,52 +1631,54 @@ GetProposedResources ( return EFI_OUT_OF_RESOURCES;
}
- Descriptor = (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *) Buffer;
+ Descriptor = (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)Buffer;
for (Index = 0; Index < TypeBus; Index++) {
ResStatus = RootBridge->ResAllocNode[Index].Status;
if (ResStatus != ResNone) {
- Descriptor->Desc = ACPI_ADDRESS_SPACE_DESCRIPTOR;
- Descriptor->Len = sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) - 3;;
- Descriptor->GenFlag = 0;
+ Descriptor->Desc = ACPI_ADDRESS_SPACE_DESCRIPTOR;
+ Descriptor->Len = sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) - 3;
+ Descriptor->GenFlag = 0;
//
// AddrRangeMin in Resource Descriptor here should be device address
// instead of host address, or else PCI bus driver cannot set correct
// address into PCI BAR registers.
// Base in ResAllocNode is a host address, so conversion is needed.
//
- Descriptor->AddrRangeMin = TO_DEVICE_ADDRESS (RootBridge->ResAllocNode[Index].Base,
- GetTranslationByResourceType (RootBridge, Index));
+ Descriptor->AddrRangeMin = TO_DEVICE_ADDRESS (
+ RootBridge->ResAllocNode[Index].Base,
+ GetTranslationByResourceType (RootBridge, Index)
+ );
Descriptor->AddrRangeMax = 0;
Descriptor->AddrTranslationOffset = (ResStatus == ResAllocated) ? EFI_RESOURCE_SATISFIED : PCI_RESOURCE_LESS;
Descriptor->AddrLen = RootBridge->ResAllocNode[Index].Length;
switch (Index) {
+ case TypeIo:
+ Descriptor->ResType = ACPI_ADDRESS_SPACE_TYPE_IO;
+ break;
- case TypeIo:
- Descriptor->ResType = ACPI_ADDRESS_SPACE_TYPE_IO;
- break;
-
- case TypePMem32:
- Descriptor->SpecificFlag = EFI_ACPI_MEMORY_RESOURCE_SPECIFIC_FLAG_CACHEABLE_PREFETCHABLE;
- case TypeMem32:
- Descriptor->ResType = ACPI_ADDRESS_SPACE_TYPE_MEM;
- Descriptor->AddrSpaceGranularity = 32;
- break;
+ case TypePMem32:
+ Descriptor->SpecificFlag = EFI_ACPI_MEMORY_RESOURCE_SPECIFIC_FLAG_CACHEABLE_PREFETCHABLE;
+ case TypeMem32:
+ Descriptor->ResType = ACPI_ADDRESS_SPACE_TYPE_MEM;
+ Descriptor->AddrSpaceGranularity = 32;
+ break;
- case TypePMem64:
- Descriptor->SpecificFlag = EFI_ACPI_MEMORY_RESOURCE_SPECIFIC_FLAG_CACHEABLE_PREFETCHABLE;
- case TypeMem64:
- Descriptor->ResType = ACPI_ADDRESS_SPACE_TYPE_MEM;
- Descriptor->AddrSpaceGranularity = 64;
- break;
+ case TypePMem64:
+ Descriptor->SpecificFlag = EFI_ACPI_MEMORY_RESOURCE_SPECIFIC_FLAG_CACHEABLE_PREFETCHABLE;
+ case TypeMem64:
+ Descriptor->ResType = ACPI_ADDRESS_SPACE_TYPE_MEM;
+ Descriptor->AddrSpaceGranularity = 64;
+ break;
}
Descriptor++;
}
}
- End = (EFI_ACPI_END_TAG_DESCRIPTOR *) Descriptor;
- End->Desc = ACPI_END_TAG_DESCRIPTOR;
- End->Checksum = 0;
+
+ End = (EFI_ACPI_END_TAG_DESCRIPTOR *)Descriptor;
+ End->Desc = ACPI_END_TAG_DESCRIPTOR;
+ End->Checksum = 0;
*Configuration = Buffer;
@@ -1567,17 +1706,17 @@ GetProposedResources ( EFI_STATUS
EFIAPI
PreprocessController (
- IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,
- IN EFI_HANDLE RootBridgeHandle,
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS PciAddress,
- IN EFI_PCI_CONTROLLER_RESOURCE_ALLOCATION_PHASE Phase
+ IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,
+ IN EFI_HANDLE RootBridgeHandle,
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS PciAddress,
+ IN EFI_PCI_CONTROLLER_RESOURCE_ALLOCATION_PHASE Phase
)
{
LIST_ENTRY *Link;
PCI_HOST_BRIDGE_INSTANCE *HostBridge;
PCI_ROOT_BRIDGE_INSTANCE *RootBridge;
- if ((UINT32) Phase > EfiPciBeforeResourceCollection) {
+ if ((UINT32)Phase > EfiPciBeforeResourceCollection) {
return EFI_INVALID_PARAMETER;
}
@@ -1585,7 +1724,8 @@ PreprocessController ( for (Link = GetFirstNode (&HostBridge->RootBridges)
; !IsNull (&HostBridge->RootBridges, Link)
; Link = GetNextNode (&HostBridge->RootBridges, Link)
- ) {
+ )
+ {
RootBridge = ROOT_BRIDGE_FROM_LINK (Link);
if (RootBridgeHandle == RootBridge->Handle) {
return EFI_SUCCESS;
diff --git a/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridge.h b/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridge.h index 755ab75..e7a30fd 100644 --- a/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridge.h +++ b/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridge.h @@ -10,7 +10,6 @@ SPDX-License-Identifier: BSD-2-Clause-Patent #ifndef _PCI_HOST_BRIDGE_H_
#define _PCI_HOST_BRIDGE_H_
-
#include <PiDxe.h>
#include <IndustryStandard/Acpi.h>
#include <Library/UefiDriverEntryPoint.h>
@@ -21,27 +20,28 @@ SPDX-License-Identifier: BSD-2-Clause-Patent #include "PciRootBridge.h"
-#define PCI_HOST_BRIDGE_SIGNATURE SIGNATURE_32 ('p', 'h', 'b', 'g')
+#define PCI_HOST_BRIDGE_SIGNATURE SIGNATURE_32 ('p', 'h', 'b', 'g')
typedef struct {
- UINTN Signature;
- EFI_HANDLE Handle;
- LIST_ENTRY RootBridges;
- BOOLEAN CanRestarted;
- EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL ResAlloc;
+ UINTN Signature;
+ EFI_HANDLE Handle;
+ LIST_ENTRY RootBridges;
+ BOOLEAN CanRestarted;
+ EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL ResAlloc;
} PCI_HOST_BRIDGE_INSTANCE;
-#define PCI_HOST_BRIDGE_FROM_THIS(a) CR (a, PCI_HOST_BRIDGE_INSTANCE, ResAlloc, PCI_HOST_BRIDGE_SIGNATURE)
+#define PCI_HOST_BRIDGE_FROM_THIS(a) CR (a, PCI_HOST_BRIDGE_INSTANCE, ResAlloc, PCI_HOST_BRIDGE_SIGNATURE)
//
// Macros to translate device address to host address and vice versa. According
// to UEFI 2.7, device address = host address + translation offset.
//
-#define TO_HOST_ADDRESS(DeviceAddress,TranslationOffset) ((DeviceAddress) - (TranslationOffset))
-#define TO_DEVICE_ADDRESS(HostAddress,TranslationOffset) ((HostAddress) + (TranslationOffset))
+#define TO_HOST_ADDRESS(DeviceAddress, TranslationOffset) ((DeviceAddress) - (TranslationOffset))
+#define TO_DEVICE_ADDRESS(HostAddress, TranslationOffset) ((HostAddress) + (TranslationOffset))
//
// Driver Entry Point
//
+
/**
Entry point of this driver.
@@ -56,13 +56,14 @@ typedef struct { EFI_STATUS
EFIAPI
InitializePciHostBridge (
- IN EFI_HANDLE ImageHandle,
- IN EFI_SYSTEM_TABLE *SystemTable
+ IN EFI_HANDLE ImageHandle,
+ IN EFI_SYSTEM_TABLE *SystemTable
);
//
// HostBridge Resource Allocation interface
//
+
/**
Enter a certain phase of the PCI enumeration process.
@@ -78,8 +79,8 @@ InitializePciHostBridge ( EFI_STATUS
EFIAPI
NotifyPhase (
- IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,
- IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PHASE Phase
+ IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,
+ IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PHASE Phase
);
/**
@@ -101,8 +102,8 @@ NotifyPhase ( EFI_STATUS
EFIAPI
GetNextRootBridge (
- IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,
- IN OUT EFI_HANDLE *RootBridgeHandle
+ IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,
+ IN OUT EFI_HANDLE *RootBridgeHandle
);
/**
@@ -124,9 +125,9 @@ GetNextRootBridge ( EFI_STATUS
EFIAPI
GetAttributes (
- IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,
- IN EFI_HANDLE RootBridgeHandle,
- OUT UINT64 *Attributes
+ IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,
+ IN EFI_HANDLE RootBridgeHandle,
+ OUT UINT64 *Attributes
);
/**
@@ -146,9 +147,9 @@ GetAttributes ( EFI_STATUS
EFIAPI
StartBusEnumeration (
- IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,
- IN EFI_HANDLE RootBridgeHandle,
- OUT VOID **Configuration
+ IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,
+ IN EFI_HANDLE RootBridgeHandle,
+ OUT VOID **Configuration
);
/**
@@ -167,9 +168,9 @@ StartBusEnumeration ( EFI_STATUS
EFIAPI
SetBusNumbers (
- IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,
- IN EFI_HANDLE RootBridgeHandle,
- IN VOID *Configuration
+ IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,
+ IN EFI_HANDLE RootBridgeHandle,
+ IN VOID *Configuration
);
/**
@@ -188,9 +189,9 @@ SetBusNumbers ( EFI_STATUS
EFIAPI
SubmitResources (
- IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,
- IN EFI_HANDLE RootBridgeHandle,
- IN VOID *Configuration
+ IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,
+ IN EFI_HANDLE RootBridgeHandle,
+ IN VOID *Configuration
);
/**
@@ -211,9 +212,9 @@ SubmitResources ( EFI_STATUS
EFIAPI
GetProposedResources (
- IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,
- IN EFI_HANDLE RootBridgeHandle,
- OUT VOID **Configuration
+ IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,
+ IN EFI_HANDLE RootBridgeHandle,
+ OUT VOID **Configuration
);
/**
@@ -233,10 +234,10 @@ GetProposedResources ( EFI_STATUS
EFIAPI
PreprocessController (
- IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,
- IN EFI_HANDLE RootBridgeHandle,
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS PciAddress,
- IN EFI_PCI_CONTROLLER_RESOURCE_ALLOCATION_PHASE Phase
+ IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,
+ IN EFI_HANDLE RootBridgeHandle,
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS PciAddress,
+ IN EFI_PCI_CONTROLLER_RESOURCE_ALLOCATION_PHASE Phase
);
/**
@@ -246,7 +247,7 @@ PreprocessController ( **/
VOID
ResourceConflict (
- IN PCI_HOST_BRIDGE_INSTANCE *HostBridge
+ IN PCI_HOST_BRIDGE_INSTANCE *HostBridge
);
/**
@@ -259,11 +260,11 @@ ResourceConflict ( **/
UINT64
GetTranslationByResourceType (
- IN PCI_ROOT_BRIDGE_INSTANCE *RootBridge,
- IN PCI_RESOURCE_TYPE ResourceType
+ IN PCI_ROOT_BRIDGE_INSTANCE *RootBridge,
+ IN PCI_RESOURCE_TYPE ResourceType
);
-extern EFI_CPU_IO2_PROTOCOL *mCpuIo;
-extern EDKII_IOMMU_PROTOCOL *mIoMmu;
+extern EFI_CPU_IO2_PROTOCOL *mCpuIo;
+extern EDKII_IOMMU_PROTOCOL *mIoMmu;
#endif
diff --git a/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostResource.h b/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostResource.h index 0f5a17d..772f4b5 100644 --- a/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostResource.h +++ b/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostResource.h @@ -6,15 +6,16 @@ Copyright (c) 1999 - 2016, Intel Corporation. All rights reserved.<BR> SPDX-License-Identifier: BSD-2-Clause-Patent
**/
+
#ifndef _PCI_HOST_RESOURCE_H_
#define _PCI_HOST_RESOURCE_H_
#include <PiDxe.h>
-#define PCI_RESOURCE_LESS 0xFFFFFFFFFFFFFFFEULL
+#define PCI_RESOURCE_LESS 0xFFFFFFFFFFFFFFFEULL
typedef enum {
- TypeIo = 0,
+ TypeIo = 0,
TypeMem32,
TypePMem32,
TypeMem64,
@@ -31,14 +32,14 @@ typedef enum { } RES_STATUS;
typedef struct {
- PCI_RESOURCE_TYPE Type;
+ PCI_RESOURCE_TYPE Type;
//
// Base is a host address
//
- UINT64 Base;
- UINT64 Length;
- UINT64 Alignment;
- RES_STATUS Status;
+ UINT64 Base;
+ UINT64 Length;
+ UINT64 Alignment;
+ RES_STATUS Status;
} PCI_RES_NODE;
#endif
diff --git a/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciRootBridge.h b/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciRootBridge.h index caa3faf..10a6200 100644 --- a/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciRootBridge.h +++ b/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciRootBridge.h @@ -31,7 +31,6 @@ SPDX-License-Identifier: BSD-2-Clause-Patent #include <Library/TimerLib.h>
#include "PciHostResource.h"
-
typedef enum {
IoOperation,
MemOperation,
@@ -40,46 +39,46 @@ typedef enum { #define MAP_INFO_SIGNATURE SIGNATURE_32 ('_', 'm', 'a', 'p')
typedef struct {
- UINT32 Signature;
- LIST_ENTRY Link;
- EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_OPERATION Operation;
- UINTN NumberOfBytes;
- UINTN NumberOfPages;
- EFI_PHYSICAL_ADDRESS HostAddress;
- EFI_PHYSICAL_ADDRESS MappedHostAddress;
+ UINT32 Signature;
+ LIST_ENTRY Link;
+ EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_OPERATION Operation;
+ UINTN NumberOfBytes;
+ UINTN NumberOfPages;
+ EFI_PHYSICAL_ADDRESS HostAddress;
+ EFI_PHYSICAL_ADDRESS MappedHostAddress;
} MAP_INFO;
-#define MAP_INFO_FROM_LINK(a) CR (a, MAP_INFO, Link, MAP_INFO_SIGNATURE)
+#define MAP_INFO_FROM_LINK(a) CR (a, MAP_INFO, Link, MAP_INFO_SIGNATURE)
-#define PCI_ROOT_BRIDGE_SIGNATURE SIGNATURE_32 ('_', 'p', 'r', 'b')
+#define PCI_ROOT_BRIDGE_SIGNATURE SIGNATURE_32 ('_', 'p', 'r', 'b')
typedef struct {
- UINT32 Signature;
- LIST_ENTRY Link;
- EFI_HANDLE Handle;
- UINT64 AllocationAttributes;
- UINT64 Attributes;
- UINT64 Supports;
- PCI_RES_NODE ResAllocNode[TypeMax];
- PCI_ROOT_BRIDGE_APERTURE Bus;
- PCI_ROOT_BRIDGE_APERTURE Io;
- PCI_ROOT_BRIDGE_APERTURE Mem;
- PCI_ROOT_BRIDGE_APERTURE PMem;
- PCI_ROOT_BRIDGE_APERTURE MemAbove4G;
- PCI_ROOT_BRIDGE_APERTURE PMemAbove4G;
- BOOLEAN DmaAbove4G;
- BOOLEAN NoExtendedConfigSpace;
- VOID *ConfigBuffer;
- EFI_DEVICE_PATH_PROTOCOL *DevicePath;
- CHAR16 *DevicePathStr;
- EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL RootBridgeIo;
-
- BOOLEAN ResourceSubmitted;
- LIST_ENTRY Maps;
+ UINT32 Signature;
+ LIST_ENTRY Link;
+ EFI_HANDLE Handle;
+ UINT64 AllocationAttributes;
+ UINT64 Attributes;
+ UINT64 Supports;
+ PCI_RES_NODE ResAllocNode[TypeMax];
+ PCI_ROOT_BRIDGE_APERTURE Bus;
+ PCI_ROOT_BRIDGE_APERTURE Io;
+ PCI_ROOT_BRIDGE_APERTURE Mem;
+ PCI_ROOT_BRIDGE_APERTURE PMem;
+ PCI_ROOT_BRIDGE_APERTURE MemAbove4G;
+ PCI_ROOT_BRIDGE_APERTURE PMemAbove4G;
+ BOOLEAN DmaAbove4G;
+ BOOLEAN NoExtendedConfigSpace;
+ VOID *ConfigBuffer;
+ EFI_DEVICE_PATH_PROTOCOL *DevicePath;
+ CHAR16 *DevicePathStr;
+ EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL RootBridgeIo;
+
+ BOOLEAN ResourceSubmitted;
+ LIST_ENTRY Maps;
} PCI_ROOT_BRIDGE_INSTANCE;
-#define ROOT_BRIDGE_FROM_THIS(a) CR (a, PCI_ROOT_BRIDGE_INSTANCE, RootBridgeIo, PCI_ROOT_BRIDGE_SIGNATURE)
+#define ROOT_BRIDGE_FROM_THIS(a) CR (a, PCI_ROOT_BRIDGE_INSTANCE, RootBridgeIo, PCI_ROOT_BRIDGE_SIGNATURE)
-#define ROOT_BRIDGE_FROM_LINK(a) CR (a, PCI_ROOT_BRIDGE_INSTANCE, Link, PCI_ROOT_BRIDGE_SIGNATURE)
+#define ROOT_BRIDGE_FROM_LINK(a) CR (a, PCI_ROOT_BRIDGE_INSTANCE, Link, PCI_ROOT_BRIDGE_SIGNATURE)
/**
Construct the Pci Root Bridge instance.
@@ -91,12 +90,13 @@ typedef struct { **/
PCI_ROOT_BRIDGE_INSTANCE *
CreateRootBridge (
- IN PCI_ROOT_BRIDGE *Bridge
+ IN PCI_ROOT_BRIDGE *Bridge
);
//
// Protocol Member Function Prototypes
//
+
/**
Poll an address in memory mapped space until an exit condition is met
@@ -286,11 +286,11 @@ RootBridgeIoIoWrite ( EFI_STATUS
EFIAPI
RootBridgeIoCopyMem (
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,
- IN UINT64 DestAddress,
- IN UINT64 SrcAddress,
- IN UINTN Count
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,
+ IN UINT64 DestAddress,
+ IN UINT64 SrcAddress,
+ IN UINTN Count
)
;
@@ -567,5 +567,5 @@ RootBridgeIoConfiguration ( )
;
-extern EFI_CPU_IO2_PROTOCOL *mCpuIo;
+extern EFI_CPU_IO2_PROTOCOL *mCpuIo;
#endif
diff --git a/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciRootBridgeIo.c b/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciRootBridgeIo.c index 2f1bed8..157a0ad 100644 --- a/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciRootBridgeIo.c +++ b/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciRootBridgeIo.c @@ -13,12 +13,12 @@ SPDX-License-Identifier: BSD-2-Clause-Patent #define NO_MAPPING (VOID *) (UINTN) -1
-#define RESOURCE_VALID(Resource) ((Resource)->Base <= (Resource)->Limit)
+#define RESOURCE_VALID(Resource) ((Resource)->Base <= (Resource)->Limit)
//
// Lookup table for increment values based on transfer widths
//
-UINT8 mInStride[] = {
+UINT8 mInStride[] = {
1, // EfiPciWidthUint8
2, // EfiPciWidthUint16
4, // EfiPciWidthUint32
@@ -36,7 +36,7 @@ UINT8 mInStride[] = { //
// Lookup table for increment values based on transfer widths
//
-UINT8 mOutStride[] = {
+UINT8 mOutStride[] = {
1, // EfiPciWidthUint8
2, // EfiPciWidthUint16
4, // EfiPciWidthUint32
@@ -61,13 +61,13 @@ UINT8 mOutStride[] = { **/
PCI_ROOT_BRIDGE_INSTANCE *
CreateRootBridge (
- IN PCI_ROOT_BRIDGE *Bridge
+ IN PCI_ROOT_BRIDGE *Bridge
)
{
- PCI_ROOT_BRIDGE_INSTANCE *RootBridge;
- PCI_RESOURCE_TYPE Index;
- CHAR16 *DevicePathStr;
- PCI_ROOT_BRIDGE_APERTURE *Aperture;
+ PCI_ROOT_BRIDGE_INSTANCE *RootBridge;
+ PCI_RESOURCE_TYPE Index;
+ CHAR16 *DevicePathStr;
+ PCI_ROOT_BRIDGE_APERTURE *Aperture;
DevicePathStr = NULL;
@@ -76,13 +76,19 @@ CreateRootBridge ( DEBUG ((DEBUG_INFO, " Support/Attr: %lx / %lx\n", Bridge->Supports, Bridge->Attributes));
DEBUG ((DEBUG_INFO, " DmaAbove4G: %s\n", Bridge->DmaAbove4G ? L"Yes" : L"No"));
DEBUG ((DEBUG_INFO, "NoExtConfSpace: %s\n", Bridge->NoExtendedConfigSpace ? L"Yes" : L"No"));
- DEBUG ((DEBUG_INFO, " AllocAttr: %lx (%s%s)\n", Bridge->AllocationAttributes,
- (Bridge->AllocationAttributes & EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM) != 0 ? L"CombineMemPMem " : L"",
- (Bridge->AllocationAttributes & EFI_PCI_HOST_BRIDGE_MEM64_DECODE) != 0 ? L"Mem64Decode" : L""
- ));
DEBUG ((
- DEBUG_INFO, " Bus: %lx - %lx Translation=%lx\n",
- Bridge->Bus.Base, Bridge->Bus.Limit, Bridge->Bus.Translation
+ DEBUG_INFO,
+ " AllocAttr: %lx (%s%s)\n",
+ Bridge->AllocationAttributes,
+ (Bridge->AllocationAttributes & EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM) != 0 ? L"CombineMemPMem " : L"",
+ (Bridge->AllocationAttributes & EFI_PCI_HOST_BRIDGE_MEM64_DECODE) != 0 ? L"Mem64Decode" : L""
+ ));
+ DEBUG ((
+ DEBUG_INFO,
+ " Bus: %lx - %lx Translation=%lx\n",
+ Bridge->Bus.Base,
+ Bridge->Bus.Limit,
+ Bridge->Bus.Translation
));
//
// Translation for bus is not supported.
@@ -93,24 +99,39 @@ CreateRootBridge ( }
DEBUG ((
- DEBUG_INFO, " Io: %lx - %lx Translation=%lx\n",
- Bridge->Io.Base, Bridge->Io.Limit, Bridge->Io.Translation
+ DEBUG_INFO,
+ " Io: %lx - %lx Translation=%lx\n",
+ Bridge->Io.Base,
+ Bridge->Io.Limit,
+ Bridge->Io.Translation
));
DEBUG ((
- DEBUG_INFO, " Mem: %lx - %lx Translation=%lx\n",
- Bridge->Mem.Base, Bridge->Mem.Limit, Bridge->Mem.Translation
+ DEBUG_INFO,
+ " Mem: %lx - %lx Translation=%lx\n",
+ Bridge->Mem.Base,
+ Bridge->Mem.Limit,
+ Bridge->Mem.Translation
));
DEBUG ((
- DEBUG_INFO, " MemAbove4G: %lx - %lx Translation=%lx\n",
- Bridge->MemAbove4G.Base, Bridge->MemAbove4G.Limit, Bridge->MemAbove4G.Translation
+ DEBUG_INFO,
+ " MemAbove4G: %lx - %lx Translation=%lx\n",
+ Bridge->MemAbove4G.Base,
+ Bridge->MemAbove4G.Limit,
+ Bridge->MemAbove4G.Translation
));
DEBUG ((
- DEBUG_INFO, " PMem: %lx - %lx Translation=%lx\n",
- Bridge->PMem.Base, Bridge->PMem.Limit, Bridge->PMem.Translation
+ DEBUG_INFO,
+ " PMem: %lx - %lx Translation=%lx\n",
+ Bridge->PMem.Base,
+ Bridge->PMem.Limit,
+ Bridge->PMem.Translation
));
DEBUG ((
- DEBUG_INFO, " PMemAbove4G: %lx - %lx Translation=%lx\n",
- Bridge->PMemAbove4G.Base, Bridge->PMemAbove4G.Limit, Bridge->PMemAbove4G.Translation
+ DEBUG_INFO,
+ " PMemAbove4G: %lx - %lx Translation=%lx\n",
+ Bridge->PMemAbove4G.Base,
+ Bridge->PMemAbove4G.Limit,
+ Bridge->PMemAbove4G.Translation
));
//
@@ -122,18 +143,21 @@ CreateRootBridge ( return NULL;
}
}
+
if (RESOURCE_VALID (&Bridge->MemAbove4G)) {
ASSERT (Bridge->MemAbove4G.Base >= SIZE_4GB);
if (Bridge->MemAbove4G.Base < SIZE_4GB) {
return NULL;
}
}
+
if (RESOURCE_VALID (&Bridge->PMem)) {
ASSERT (Bridge->PMem.Limit < SIZE_4GB);
if (Bridge->PMem.Limit >= SIZE_4GB) {
return NULL;
}
}
+
if (RESOURCE_VALID (&Bridge->PMemAbove4G)) {
ASSERT (Bridge->PMemAbove4G.Base >= SIZE_4GB);
if (Bridge->PMemAbove4G.Base < SIZE_4GB) {
@@ -174,17 +198,17 @@ CreateRootBridge ( RootBridge = AllocateZeroPool (sizeof (PCI_ROOT_BRIDGE_INSTANCE));
ASSERT (RootBridge != NULL);
- RootBridge->Signature = PCI_ROOT_BRIDGE_SIGNATURE;
- RootBridge->Supports = Bridge->Supports;
- RootBridge->Attributes = Bridge->Attributes;
- RootBridge->DmaAbove4G = Bridge->DmaAbove4G;
+ RootBridge->Signature = PCI_ROOT_BRIDGE_SIGNATURE;
+ RootBridge->Supports = Bridge->Supports;
+ RootBridge->Attributes = Bridge->Attributes;
+ RootBridge->DmaAbove4G = Bridge->DmaAbove4G;
RootBridge->NoExtendedConfigSpace = Bridge->NoExtendedConfigSpace;
- RootBridge->AllocationAttributes = Bridge->AllocationAttributes;
- RootBridge->DevicePath = DuplicateDevicePath (Bridge->DevicePath);
- RootBridge->DevicePathStr = DevicePathStr;
- RootBridge->ConfigBuffer = AllocatePool (
- TypeMax * sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) + sizeof (EFI_ACPI_END_TAG_DESCRIPTOR)
- );
+ RootBridge->AllocationAttributes = Bridge->AllocationAttributes;
+ RootBridge->DevicePath = DuplicateDevicePath (Bridge->DevicePath);
+ RootBridge->DevicePathStr = DevicePathStr;
+ RootBridge->ConfigBuffer = AllocatePool (
+ TypeMax * sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) + sizeof (EFI_ACPI_END_TAG_DESCRIPTOR)
+ );
ASSERT (RootBridge->ConfigBuffer != NULL);
InitializeListHead (&RootBridge->Maps);
@@ -197,37 +221,40 @@ CreateRootBridge ( for (Index = TypeIo; Index < TypeMax; Index++) {
switch (Index) {
- case TypeBus:
- Aperture = &RootBridge->Bus;
- break;
- case TypeIo:
- Aperture = &RootBridge->Io;
- break;
- case TypeMem32:
- Aperture = &RootBridge->Mem;
- break;
- case TypeMem64:
- Aperture = &RootBridge->MemAbove4G;
- break;
- case TypePMem32:
- Aperture = &RootBridge->PMem;
- break;
- case TypePMem64:
- Aperture = &RootBridge->PMemAbove4G;
- break;
- default:
- ASSERT (FALSE);
- Aperture = NULL;
- break;
+ case TypeBus:
+ Aperture = &RootBridge->Bus;
+ break;
+ case TypeIo:
+ Aperture = &RootBridge->Io;
+ break;
+ case TypeMem32:
+ Aperture = &RootBridge->Mem;
+ break;
+ case TypeMem64:
+ Aperture = &RootBridge->MemAbove4G;
+ break;
+ case TypePMem32:
+ Aperture = &RootBridge->PMem;
+ break;
+ case TypePMem64:
+ Aperture = &RootBridge->PMemAbove4G;
+ break;
+ default:
+ ASSERT (FALSE);
+ Aperture = NULL;
+ break;
}
- RootBridge->ResAllocNode[Index].Type = Index;
+
+ RootBridge->ResAllocNode[Index].Type = Index;
if (Bridge->ResourceAssigned && (Aperture->Limit >= Aperture->Base)) {
//
// Base in ResAllocNode is a host address, while Base in Aperture is a
// device address.
//
- RootBridge->ResAllocNode[Index].Base = TO_HOST_ADDRESS (Aperture->Base,
- Aperture->Translation);
+ RootBridge->ResAllocNode[Index].Base = TO_HOST_ADDRESS (
+ Aperture->Base,
+ Aperture->Translation
+ );
RootBridge->ResAllocNode[Index].Length = Aperture->Limit - Aperture->Base + 1;
RootBridge->ResAllocNode[Index].Status = ResAllocated;
} else {
@@ -325,7 +352,7 @@ RootBridgeIoCheckParameter ( //
// Check to see if Width is in the valid range
//
- if ((UINT32) Width >= EfiPciWidthMaximum) {
+ if ((UINT32)Width >= EfiPciWidthMaximum) {
return EFI_INVALID_PARAMETER;
}
@@ -333,11 +360,11 @@ RootBridgeIoCheckParameter ( // For FIFO type, the device address won't increase during the access,
// so treat Count as 1
//
- if (Width >= EfiPciWidthFifoUint8 && Width <= EfiPciWidthFifoUint64) {
+ if ((Width >= EfiPciWidthFifoUint8) && (Width <= EfiPciWidthFifoUint64)) {
Count = 1;
}
- Width = (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) (Width & 0x03);
+ Width = (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH)(Width & 0x03);
Size = 1 << Width;
//
@@ -382,23 +409,26 @@ RootBridgeIoCheckParameter ( //
if (Address + Length <= 0x1000) {
if ((RootBridge->Attributes & (
- EFI_PCI_ATTRIBUTE_ISA_IO | EFI_PCI_ATTRIBUTE_VGA_PALETTE_IO | EFI_PCI_ATTRIBUTE_VGA_IO |
- EFI_PCI_ATTRIBUTE_IDE_PRIMARY_IO | EFI_PCI_ATTRIBUTE_IDE_SECONDARY_IO |
- EFI_PCI_ATTRIBUTE_ISA_IO_16 | EFI_PCI_ATTRIBUTE_VGA_PALETTE_IO_16 | EFI_PCI_ATTRIBUTE_VGA_IO_16)) != 0) {
+ EFI_PCI_ATTRIBUTE_ISA_IO | EFI_PCI_ATTRIBUTE_VGA_PALETTE_IO | EFI_PCI_ATTRIBUTE_VGA_IO |
+ EFI_PCI_ATTRIBUTE_IDE_PRIMARY_IO | EFI_PCI_ATTRIBUTE_IDE_SECONDARY_IO |
+ EFI_PCI_ATTRIBUTE_ISA_IO_16 | EFI_PCI_ATTRIBUTE_VGA_PALETTE_IO_16 | EFI_PCI_ATTRIBUTE_VGA_IO_16)) != 0)
+ {
return EFI_SUCCESS;
}
}
- Base = RootBridge->Io.Base;
+
+ Base = RootBridge->Io.Base;
Limit = RootBridge->Io.Limit;
} else if (OperationType == MemOperation) {
//
// Allow Legacy MMIO access
//
- if ((Address >= 0xA0000) && (Address + Length) <= 0xC0000) {
+ if ((Address >= 0xA0000) && ((Address + Length) <= 0xC0000)) {
if ((RootBridge->Attributes & EFI_PCI_ATTRIBUTE_VGA_MEMORY) != 0) {
return EFI_SUCCESS;
}
}
+
//
// By comparing the Address against Limit we know which range to be used
// for checking
@@ -417,14 +447,16 @@ RootBridgeIoCheckParameter ( Limit = RootBridge->PMemAbove4G.Limit;
}
} else {
- PciRbAddr = (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS*) &Address;
- if (PciRbAddr->Bus < RootBridge->Bus.Base ||
- PciRbAddr->Bus > RootBridge->Bus.Limit) {
+ PciRbAddr = (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS *)&Address;
+ if ((PciRbAddr->Bus < RootBridge->Bus.Base) ||
+ (PciRbAddr->Bus > RootBridge->Bus.Limit))
+ {
return EFI_INVALID_PARAMETER;
}
- if (PciRbAddr->Device > PCI_MAX_DEVICE ||
- PciRbAddr->Function > PCI_MAX_FUNC) {
+ if ((PciRbAddr->Device > PCI_MAX_DEVICE) ||
+ (PciRbAddr->Function > PCI_MAX_FUNC))
+ {
return EFI_INVALID_PARAMETER;
}
@@ -433,12 +465,13 @@ RootBridgeIoCheckParameter ( } else {
Address = PciRbAddr->Register;
}
- Base = 0;
+
+ Base = 0;
Limit = RootBridge->NoExtendedConfigSpace ? 0xFF : 0xFFF;
}
if (Address < Base) {
- return EFI_INVALID_PARAMETER;
+ return EFI_INVALID_PARAMETER;
}
if (Address + Length > Limit + 1) {
@@ -462,18 +495,18 @@ RootBridgeIoCheckParameter ( **/
EFI_STATUS
RootBridgeIoGetMemTranslationByAddress (
- IN PCI_ROOT_BRIDGE_INSTANCE *RootBridge,
- IN UINT64 Address,
- IN OUT UINT64 *Translation
+ IN PCI_ROOT_BRIDGE_INSTANCE *RootBridge,
+ IN UINT64 Address,
+ IN OUT UINT64 *Translation
)
{
- if (Address >= RootBridge->Mem.Base && Address <= RootBridge->Mem.Limit) {
+ if ((Address >= RootBridge->Mem.Base) && (Address <= RootBridge->Mem.Limit)) {
*Translation = RootBridge->Mem.Translation;
- } else if (Address >= RootBridge->PMem.Base && Address <= RootBridge->PMem.Limit) {
+ } else if ((Address >= RootBridge->PMem.Base) && (Address <= RootBridge->PMem.Limit)) {
*Translation = RootBridge->PMem.Translation;
- } else if (Address >= RootBridge->MemAbove4G.Base && Address <= RootBridge->MemAbove4G.Limit) {
+ } else if ((Address >= RootBridge->MemAbove4G.Base) && (Address <= RootBridge->MemAbove4G.Limit)) {
*Translation = RootBridge->MemAbove4G.Translation;
- } else if (Address >= RootBridge->PMemAbove4G.Base && Address <= RootBridge->PMemAbove4G.Limit) {
+ } else if ((Address >= RootBridge->PMemAbove4G.Base) && (Address <= RootBridge->PMemAbove4G.Limit)) {
*Translation = RootBridge->PMemAbove4G.Translation;
} else {
return EFI_INVALID_PARAMETER;
@@ -495,15 +528,16 @@ RootBridgeIoGetMemTranslationByAddress ( **/
UINT64
MultThenDivU64x64x32 (
- IN UINT64 Multiplicand,
- IN UINT64 Multiplier,
- IN UINT32 Divisor,
- OUT UINT32 *Remainder OPTIONAL
+ IN UINT64 Multiplicand,
+ IN UINT64 Multiplier,
+ IN UINT32 Divisor,
+ OUT UINT32 *Remainder OPTIONAL
)
{
- UINT64 Uint64;
- UINT32 LocalRemainder;
- UINT32 Uint32;
+ UINT64 Uint64;
+ UINT32 LocalRemainder;
+ UINT32 Uint32;
+
if (Multiplicand > DivU64x64Remainder (MAX_UINT64, Multiplier, NULL)) {
//
// Make sure Multiplicand is the bigger one.
@@ -513,6 +547,7 @@ MultThenDivU64x64x32 ( Multiplicand = Multiplier;
Multiplier = Uint64;
}
+
//
// Because Multiplicand * Multiplier overflows,
// Multiplicand * Multiplier / Divisor
@@ -525,6 +560,7 @@ MultThenDivU64x64x32 ( if ((Multiplicand & 0x1) == 1) {
Uint64 += DivU64x32Remainder (Multiplier, Divisor, &Uint32);
}
+
return Uint64 + DivU64x32Remainder (Uint32 + LShiftU64 (LocalRemainder, 1), Divisor, Remainder);
} else {
return DivU64x32Remainder (MultU64x64 (Multiplicand, Multiplier), Divisor, Remainder);
@@ -553,7 +589,7 @@ GetElapsedTick ( UINT64 PreviousTick;
PreviousTick = *CurrentTick;
- *CurrentTick = GetPerformanceCounter();
+ *CurrentTick = GetPerformanceCounter ();
if (StartTick < EndTick) {
return *CurrentTick - PreviousTick;
} else {
@@ -638,20 +674,21 @@ RootBridgeIoPollMem ( if (Delay == 0) {
return EFI_SUCCESS;
-
} else {
//
// NumberOfTicks = Frenquency * Delay / EFI_TIMER_PERIOD_SECONDS(1)
//
Frequency = GetPerformanceCounterProperties (&StartTick, &EndTick);
- NumberOfTicks = MultThenDivU64x64x32 (Frequency, Delay, (UINT32)EFI_TIMER_PERIOD_SECONDS(1), &Remainder);
- if (Remainder >= (UINTN)EFI_TIMER_PERIOD_SECONDS(1) / 2) {
+ NumberOfTicks = MultThenDivU64x64x32 (Frequency, Delay, (UINT32)EFI_TIMER_PERIOD_SECONDS (1), &Remainder);
+ if (Remainder >= (UINTN)EFI_TIMER_PERIOD_SECONDS (1) / 2) {
NumberOfTicks++;
}
- for ( ElapsedTick = 0, CurrentTick = GetPerformanceCounter()
- ; ElapsedTick <= NumberOfTicks
- ; ElapsedTick += GetElapsedTick (&CurrentTick, StartTick, EndTick)
- ) {
+
+ for ( ElapsedTick = 0, CurrentTick = GetPerformanceCounter ()
+ ; ElapsedTick <= NumberOfTicks
+ ; ElapsedTick += GetElapsedTick (&CurrentTick, StartTick, EndTick)
+ )
+ {
Status = This->Mem.Read (This, Width, Address, 1, Result);
if (EFI_ERROR (Status)) {
return Status;
@@ -662,6 +699,7 @@ RootBridgeIoPollMem ( }
}
}
+
return EFI_TIMEOUT;
}
@@ -734,26 +772,28 @@ RootBridgeIoPollIo ( if (EFI_ERROR (Status)) {
return Status;
}
+
if ((*Result & Mask) == Value) {
return EFI_SUCCESS;
}
if (Delay == 0) {
return EFI_SUCCESS;
-
} else {
//
// NumberOfTicks = Frenquency * Delay / EFI_TIMER_PERIOD_SECONDS(1)
//
Frequency = GetPerformanceCounterProperties (&StartTick, &EndTick);
- NumberOfTicks = MultThenDivU64x64x32 (Frequency, Delay, (UINT32)EFI_TIMER_PERIOD_SECONDS(1), &Remainder);
- if (Remainder >= (UINTN)EFI_TIMER_PERIOD_SECONDS(1) / 2) {
+ NumberOfTicks = MultThenDivU64x64x32 (Frequency, Delay, (UINT32)EFI_TIMER_PERIOD_SECONDS (1), &Remainder);
+ if (Remainder >= (UINTN)EFI_TIMER_PERIOD_SECONDS (1) / 2) {
NumberOfTicks++;
}
- for ( ElapsedTick = 0, CurrentTick = GetPerformanceCounter()
- ; ElapsedTick <= NumberOfTicks
- ; ElapsedTick += GetElapsedTick (&CurrentTick, StartTick, EndTick)
- ) {
+
+ for ( ElapsedTick = 0, CurrentTick = GetPerformanceCounter ()
+ ; ElapsedTick <= NumberOfTicks
+ ; ElapsedTick += GetElapsedTick (&CurrentTick, StartTick, EndTick)
+ )
+ {
Status = This->Io.Read (This, Width, Address, 1, Result);
if (EFI_ERROR (Status)) {
return Status;
@@ -764,6 +804,7 @@ RootBridgeIoPollIo ( }
}
}
+
return EFI_TIMEOUT;
}
@@ -804,26 +845,37 @@ RootBridgeIoMemRead ( OUT VOID *Buffer
)
{
- EFI_STATUS Status;
- PCI_ROOT_BRIDGE_INSTANCE *RootBridge;
- UINT64 Translation;
+ EFI_STATUS Status;
+ PCI_ROOT_BRIDGE_INSTANCE *RootBridge;
+ UINT64 Translation;
- Status = RootBridgeIoCheckParameter (This, MemOperation, Width, Address,
- Count, Buffer);
+ Status = RootBridgeIoCheckParameter (
+ This,
+ MemOperation,
+ Width,
+ Address,
+ Count,
+ Buffer
+ );
if (EFI_ERROR (Status)) {
return Status;
}
RootBridge = ROOT_BRIDGE_FROM_THIS (This);
- Status = RootBridgeIoGetMemTranslationByAddress (RootBridge, Address, &Translation);
+ Status = RootBridgeIoGetMemTranslationByAddress (RootBridge, Address, &Translation);
if (EFI_ERROR (Status)) {
return Status;
}
// Address passed to CpuIo->Mem.Read needs to be a host address instead of
// device address.
- return mCpuIo->Mem.Read (mCpuIo, (EFI_CPU_IO_PROTOCOL_WIDTH) Width,
- TO_HOST_ADDRESS (Address, Translation), Count, Buffer);
+ return mCpuIo->Mem.Read (
+ mCpuIo,
+ (EFI_CPU_IO_PROTOCOL_WIDTH)Width,
+ TO_HOST_ADDRESS (Address, Translation),
+ Count,
+ Buffer
+ );
}
/**
@@ -863,26 +915,37 @@ RootBridgeIoMemWrite ( IN VOID *Buffer
)
{
- EFI_STATUS Status;
- PCI_ROOT_BRIDGE_INSTANCE *RootBridge;
- UINT64 Translation;
+ EFI_STATUS Status;
+ PCI_ROOT_BRIDGE_INSTANCE *RootBridge;
+ UINT64 Translation;
- Status = RootBridgeIoCheckParameter (This, MemOperation, Width, Address,
- Count, Buffer);
+ Status = RootBridgeIoCheckParameter (
+ This,
+ MemOperation,
+ Width,
+ Address,
+ Count,
+ Buffer
+ );
if (EFI_ERROR (Status)) {
return Status;
}
RootBridge = ROOT_BRIDGE_FROM_THIS (This);
- Status = RootBridgeIoGetMemTranslationByAddress (RootBridge, Address, &Translation);
+ Status = RootBridgeIoGetMemTranslationByAddress (RootBridge, Address, &Translation);
if (EFI_ERROR (Status)) {
return Status;
}
// Address passed to CpuIo->Mem.Write needs to be a host address instead of
// device address.
- return mCpuIo->Mem.Write (mCpuIo, (EFI_CPU_IO_PROTOCOL_WIDTH) Width,
- TO_HOST_ADDRESS (Address, Translation), Count, Buffer);
+ return mCpuIo->Mem.Write (
+ mCpuIo,
+ (EFI_CPU_IO_PROTOCOL_WIDTH)Width,
+ TO_HOST_ADDRESS (Address, Translation),
+ Count,
+ Buffer
+ );
}
/**
@@ -916,12 +979,16 @@ RootBridgeIoIoRead ( OUT VOID *Buffer
)
{
- EFI_STATUS Status;
- PCI_ROOT_BRIDGE_INSTANCE *RootBridge;
+ EFI_STATUS Status;
+ PCI_ROOT_BRIDGE_INSTANCE *RootBridge;
Status = RootBridgeIoCheckParameter (
- This, IoOperation, Width,
- Address, Count, Buffer
+ This,
+ IoOperation,
+ Width,
+ Address,
+ Count,
+ Buffer
);
if (EFI_ERROR (Status)) {
return Status;
@@ -931,8 +998,13 @@ RootBridgeIoIoRead ( // Address passed to CpuIo->Io.Read needs to be a host address instead of
// device address.
- return mCpuIo->Io.Read (mCpuIo, (EFI_CPU_IO_PROTOCOL_WIDTH) Width,
- TO_HOST_ADDRESS (Address, RootBridge->Io.Translation), Count, Buffer);
+ return mCpuIo->Io.Read (
+ mCpuIo,
+ (EFI_CPU_IO_PROTOCOL_WIDTH)Width,
+ TO_HOST_ADDRESS (Address, RootBridge->Io.Translation),
+ Count,
+ Buffer
+ );
}
/**
@@ -959,19 +1031,23 @@ RootBridgeIoIoRead ( EFI_STATUS
EFIAPI
RootBridgeIoIoWrite (
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,
- IN UINT64 Address,
- IN UINTN Count,
- IN VOID *Buffer
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,
+ IN UINT64 Address,
+ IN UINTN Count,
+ IN VOID *Buffer
)
{
- EFI_STATUS Status;
- PCI_ROOT_BRIDGE_INSTANCE *RootBridge;
+ EFI_STATUS Status;
+ PCI_ROOT_BRIDGE_INSTANCE *RootBridge;
Status = RootBridgeIoCheckParameter (
- This, IoOperation, Width,
- Address, Count, Buffer
+ This,
+ IoOperation,
+ Width,
+ Address,
+ Count,
+ Buffer
);
if (EFI_ERROR (Status)) {
return Status;
@@ -981,8 +1057,13 @@ RootBridgeIoIoWrite ( // Address passed to CpuIo->Io.Write needs to be a host address instead of
// device address.
- return mCpuIo->Io.Write (mCpuIo, (EFI_CPU_IO_PROTOCOL_WIDTH) Width,
- TO_HOST_ADDRESS (Address, RootBridge->Io.Translation), Count, Buffer);
+ return mCpuIo->Io.Write (
+ mCpuIo,
+ (EFI_CPU_IO_PROTOCOL_WIDTH)Width,
+ TO_HOST_ADDRESS (Address, RootBridge->Io.Translation),
+ Count,
+ Buffer
+ );
}
/**
@@ -1019,11 +1100,11 @@ RootBridgeIoIoWrite ( EFI_STATUS
EFIAPI
RootBridgeIoCopyMem (
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,
- IN UINT64 DestAddress,
- IN UINT64 SrcAddress,
- IN UINTN Count
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,
+ IN UINT64 DestAddress,
+ IN UINT64 SrcAddress,
+ IN UINTN Count
)
{
EFI_STATUS Status;
@@ -1032,7 +1113,7 @@ RootBridgeIoCopyMem ( UINTN Index;
UINT64 Result;
- if ((UINT32) Width > EfiPciWidthUint64) {
+ if ((UINT32)Width > EfiPciWidthUint64) {
return EFI_INVALID_PARAMETER;
}
@@ -1040,13 +1121,14 @@ RootBridgeIoCopyMem ( return EFI_SUCCESS;
}
- Stride = (UINTN) (1 << Width);
+ Stride = (UINTN)(1 << Width);
Forward = TRUE;
if ((DestAddress > SrcAddress) &&
- (DestAddress < (SrcAddress + Count * Stride))) {
- Forward = FALSE;
- SrcAddress = SrcAddress + (Count - 1) * Stride;
+ (DestAddress < (SrcAddress + Count * Stride)))
+ {
+ Forward = FALSE;
+ SrcAddress = SrcAddress + (Count - 1) * Stride;
DestAddress = DestAddress + (Count - 1) * Stride;
}
@@ -1061,6 +1143,7 @@ RootBridgeIoCopyMem ( if (EFI_ERROR (Status)) {
return Status;
}
+
Status = RootBridgeIoMemWrite (
This,
Width,
@@ -1071,18 +1154,19 @@ RootBridgeIoCopyMem ( if (EFI_ERROR (Status)) {
return Status;
}
+
if (Forward) {
- SrcAddress += Stride;
+ SrcAddress += Stride;
DestAddress += Stride;
} else {
- SrcAddress -= Stride;
+ SrcAddress -= Stride;
DestAddress -= Stride;
}
}
+
return EFI_SUCCESS;
}
-
/**
PCI configuration space access.
@@ -1101,12 +1185,12 @@ RootBridgeIoCopyMem ( EFI_STATUS
EFIAPI
RootBridgeIoPciAccess (
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,
- IN BOOLEAN Read,
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,
- IN UINT64 Address,
- IN UINTN Count,
- IN OUT VOID *Buffer
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,
+ IN BOOLEAN Read,
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,
+ IN UINT64 Address,
+ IN UINTN Count,
+ IN OUT VOID *Buffer
)
{
EFI_STATUS Status;
@@ -1145,7 +1229,7 @@ RootBridgeIoPciAccess ( //
InStride = mInStride[Width];
OutStride = mOutStride[Width];
- Size = (UINTN) (1 << (Width & 0x03));
+ Size = (UINTN)(1 << (Width & 0x03));
for (Uint8Buffer = Buffer; Count > 0; Address += InStride, Uint8Buffer += OutStride, Count--) {
if (Read) {
PciSegmentReadBuffer (Address, Size, Uint8Buffer);
@@ -1153,6 +1237,7 @@ RootBridgeIoPciAccess ( PciSegmentWriteBuffer (Address, Size, Uint8Buffer);
}
}
+
return EFI_SUCCESS;
}
@@ -1173,11 +1258,11 @@ RootBridgeIoPciAccess ( EFI_STATUS
EFIAPI
RootBridgeIoPciRead (
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,
- IN UINT64 Address,
- IN UINTN Count,
- IN OUT VOID *Buffer
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,
+ IN UINT64 Address,
+ IN UINTN Count,
+ IN OUT VOID *Buffer
)
{
return RootBridgeIoPciAccess (This, TRUE, Width, Address, Count, Buffer);
@@ -1200,11 +1285,11 @@ RootBridgeIoPciRead ( EFI_STATUS
EFIAPI
RootBridgeIoPciWrite (
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,
- IN UINT64 Address,
- IN UINTN Count,
- IN OUT VOID *Buffer
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,
+ IN UINT64 Address,
+ IN UINTN Count,
+ IN OUT VOID *Buffer
)
{
return RootBridgeIoPciAccess (This, FALSE, Width, Address, Count, Buffer);
@@ -1242,20 +1327,21 @@ RootBridgeIoMap ( OUT VOID **Mapping
)
{
- EFI_STATUS Status;
- PCI_ROOT_BRIDGE_INSTANCE *RootBridge;
- EFI_PHYSICAL_ADDRESS PhysicalAddress;
- MAP_INFO *MapInfo;
+ EFI_STATUS Status;
+ PCI_ROOT_BRIDGE_INSTANCE *RootBridge;
+ EFI_PHYSICAL_ADDRESS PhysicalAddress;
+ MAP_INFO *MapInfo;
- if (HostAddress == NULL || NumberOfBytes == NULL || DeviceAddress == NULL ||
- Mapping == NULL) {
+ if ((HostAddress == NULL) || (NumberOfBytes == NULL) || (DeviceAddress == NULL) ||
+ (Mapping == NULL))
+ {
return EFI_INVALID_PARAMETER;
}
//
// Make sure that Operation is valid
//
- if ((UINT32) Operation >= EfiPciOperationMaximum) {
+ if ((UINT32)Operation >= EfiPciOperationMaximum) {
return EFI_INVALID_PARAMETER;
}
@@ -1267,12 +1353,13 @@ RootBridgeIoMap ( // Clear 64bit support
//
if (Operation > EfiPciOperationBusMasterCommonBuffer) {
- Operation = (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_OPERATION) (Operation - EfiPciOperationBusMasterRead64);
+ Operation = (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_OPERATION)(Operation - EfiPciOperationBusMasterRead64);
}
}
+
Status = mIoMmu->Map (
mIoMmu,
- (EDKII_IOMMU_OPERATION) Operation,
+ (EDKII_IOMMU_OPERATION)Operation,
HostAddress,
NumberOfBytes,
DeviceAddress,
@@ -1281,21 +1368,22 @@ RootBridgeIoMap ( return Status;
}
- PhysicalAddress = (EFI_PHYSICAL_ADDRESS) (UINTN) HostAddress;
+ PhysicalAddress = (EFI_PHYSICAL_ADDRESS)(UINTN)HostAddress;
if ((!RootBridge->DmaAbove4G ||
- (Operation != EfiPciOperationBusMasterRead64 &&
- Operation != EfiPciOperationBusMasterWrite64 &&
- Operation != EfiPciOperationBusMasterCommonBuffer64)) &&
- ((PhysicalAddress + *NumberOfBytes) > SIZE_4GB)) {
-
+ ((Operation != EfiPciOperationBusMasterRead64) &&
+ (Operation != EfiPciOperationBusMasterWrite64) &&
+ (Operation != EfiPciOperationBusMasterCommonBuffer64))) &&
+ ((PhysicalAddress + *NumberOfBytes) > SIZE_4GB))
+ {
//
// If the root bridge or the device cannot handle performing DMA above
// 4GB but any part of the DMA transfer being mapped is above 4GB, then
// map the DMA transfer to a buffer below 4GB.
//
- if (Operation == EfiPciOperationBusMasterCommonBuffer ||
- Operation == EfiPciOperationBusMasterCommonBuffer64) {
+ if ((Operation == EfiPciOperationBusMasterCommonBuffer) ||
+ (Operation == EfiPciOperationBusMasterCommonBuffer64))
+ {
//
// Common Buffer operations can not be remapped. If the common buffer
// if above 4GB, then it is not possible to generate a mapping, so return
@@ -1344,11 +1432,12 @@ RootBridgeIoMap ( // then copy the contents of the real buffer into the mapped buffer
// so the Bus Master can read the contents of the real buffer.
//
- if (Operation == EfiPciOperationBusMasterRead ||
- Operation == EfiPciOperationBusMasterRead64) {
+ if ((Operation == EfiPciOperationBusMasterRead) ||
+ (Operation == EfiPciOperationBusMasterRead64))
+ {
CopyMem (
- (VOID *) (UINTN) MapInfo->MappedHostAddress,
- (VOID *) (UINTN) MapInfo->HostAddress,
+ (VOID *)(UINTN)MapInfo->MappedHostAddress,
+ (VOID *)(UINTN)MapInfo->HostAddress,
MapInfo->NumberOfBytes
);
}
@@ -1362,7 +1451,7 @@ RootBridgeIoMap ( //
// Return a pointer to the MAP_INFO structure in Mapping
//
- *Mapping = MapInfo;
+ *Mapping = MapInfo;
} else {
//
// If the root bridge CAN handle performing DMA above 4GB or
@@ -1400,9 +1489,9 @@ RootBridgeIoUnmap ( IN VOID *Mapping
)
{
- MAP_INFO *MapInfo;
- LIST_ENTRY *Link;
- PCI_ROOT_BRIDGE_INSTANCE *RootBridge;
+ MAP_INFO *MapInfo;
+ LIST_ENTRY *Link;
+ PCI_ROOT_BRIDGE_INSTANCE *RootBridge;
EFI_STATUS Status;
if (mIoMmu != NULL) {
@@ -1428,18 +1517,21 @@ RootBridgeIoUnmap ( for (Link = GetFirstNode (&RootBridge->Maps)
; !IsNull (&RootBridge->Maps, Link)
; Link = GetNextNode (&RootBridge->Maps, Link)
- ) {
+ )
+ {
MapInfo = MAP_INFO_FROM_LINK (Link);
if (MapInfo == Mapping) {
break;
}
}
+
//
// Mapping is not a valid value returned by Map()
//
if (MapInfo != Mapping) {
return EFI_INVALID_PARAMETER;
}
+
RemoveEntryList (&MapInfo->Link);
//
@@ -1447,11 +1539,12 @@ RootBridgeIoUnmap ( // then copy the contents of the mapped buffer into the real buffer
// so the processor can read the contents of the real buffer.
//
- if (MapInfo->Operation == EfiPciOperationBusMasterWrite ||
- MapInfo->Operation == EfiPciOperationBusMasterWrite64) {
+ if ((MapInfo->Operation == EfiPciOperationBusMasterWrite) ||
+ (MapInfo->Operation == EfiPciOperationBusMasterWrite64))
+ {
CopyMem (
- (VOID *) (UINTN) MapInfo->HostAddress,
- (VOID *) (UINTN) MapInfo->MappedHostAddress,
+ (VOID *)(UINTN)MapInfo->HostAddress,
+ (VOID *)(UINTN)MapInfo->MappedHostAddress,
MapInfo->NumberOfBytes
);
}
@@ -1524,8 +1617,9 @@ RootBridgeIoAllocateBuffer ( // The only valid memory types are EfiBootServicesData and
// EfiRuntimeServicesData
//
- if (MemoryType != EfiBootServicesData &&
- MemoryType != EfiRuntimeServicesData) {
+ if ((MemoryType != EfiBootServicesData) &&
+ (MemoryType != EfiRuntimeServicesData))
+ {
return EFI_INVALID_PARAMETER;
}
@@ -1536,8 +1630,9 @@ RootBridgeIoAllocateBuffer ( //
// Clear DUAL_ADDRESS_CYCLE
//
- Attributes &= ~((UINT64) EFI_PCI_ATTRIBUTE_DUAL_ADDRESS_CYCLE);
+ Attributes &= ~((UINT64)EFI_PCI_ATTRIBUTE_DUAL_ADDRESS_CYCLE);
}
+
Status = mIoMmu->AllocateBuffer (
mIoMmu,
Type,
@@ -1551,13 +1646,15 @@ RootBridgeIoAllocateBuffer ( AllocateType = AllocateAnyPages;
if (!RootBridge->DmaAbove4G ||
- (Attributes & EFI_PCI_ATTRIBUTE_DUAL_ADDRESS_CYCLE) == 0) {
+ ((Attributes & EFI_PCI_ATTRIBUTE_DUAL_ADDRESS_CYCLE) == 0))
+ {
//
// Limit allocations to memory below 4GB
//
AllocateType = AllocateMaxAddress;
- PhysicalAddress = (EFI_PHYSICAL_ADDRESS) (SIZE_4GB - 1);
+ PhysicalAddress = (EFI_PHYSICAL_ADDRESS)(SIZE_4GB - 1);
}
+
Status = gBS->AllocatePages (
AllocateType,
MemoryType,
@@ -1565,7 +1662,7 @@ RootBridgeIoAllocateBuffer ( &PhysicalAddress
);
if (!EFI_ERROR (Status)) {
- *HostAddress = (VOID *) (UINTN) PhysicalAddress;
+ *HostAddress = (VOID *)(UINTN)PhysicalAddress;
}
return Status;
@@ -1593,7 +1690,7 @@ RootBridgeIoFreeBuffer ( OUT VOID *HostAddress
)
{
- EFI_STATUS Status;
+ EFI_STATUS Status;
if (mIoMmu != NULL) {
Status = mIoMmu->FreeBuffer (
@@ -1604,7 +1701,7 @@ RootBridgeIoFreeBuffer ( return Status;
}
- return gBS->FreePages ((EFI_PHYSICAL_ADDRESS) (UINTN) HostAddress, Pages);
+ return gBS->FreePages ((EFI_PHYSICAL_ADDRESS)(UINTN)HostAddress, Pages);
}
/**
@@ -1631,7 +1728,7 @@ RootBridgeIoFreeBuffer ( EFI_STATUS
EFIAPI
RootBridgeIoFlush (
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This
)
{
return EFI_SUCCESS;
@@ -1667,9 +1764,9 @@ RootBridgeIoGetAttributes ( OUT UINT64 *Attributes
)
{
- PCI_ROOT_BRIDGE_INSTANCE *RootBridge;
+ PCI_ROOT_BRIDGE_INSTANCE *RootBridge;
- if (Attributes == NULL && Supported == NULL) {
+ if ((Attributes == NULL) && (Supported == NULL)) {
return EFI_INVALID_PARAMETER;
}
@@ -1678,7 +1775,7 @@ RootBridgeIoGetAttributes ( // Set the return value for Supported and Attributes
//
if (Supported != NULL) {
- *Supported = RootBridge->Supports;
+ *Supported = RootBridge->Supports;
}
if (Attributes != NULL) {
@@ -1733,7 +1830,7 @@ RootBridgeIoSetAttributes ( IN OUT UINT64 *ResourceLength
)
{
- PCI_ROOT_BRIDGE_INSTANCE *RootBridge;
+ PCI_ROOT_BRIDGE_INSTANCE *RootBridge;
RootBridge = ROOT_BRIDGE_FROM_THIS (This);
@@ -1773,15 +1870,15 @@ RootBridgeIoSetAttributes ( EFI_STATUS
EFIAPI
RootBridgeIoConfiguration (
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,
- OUT VOID **Resources
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,
+ OUT VOID **Resources
)
{
- PCI_RESOURCE_TYPE Index;
- PCI_ROOT_BRIDGE_INSTANCE *RootBridge;
- PCI_RES_NODE *ResAllocNode;
- EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Descriptor;
- EFI_ACPI_END_TAG_DESCRIPTOR *End;
+ PCI_RESOURCE_TYPE Index;
+ PCI_ROOT_BRIDGE_INSTANCE *RootBridge;
+ PCI_RES_NODE *ResAllocNode;
+ EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Descriptor;
+ EFI_ACPI_END_TAG_DESCRIPTOR *End;
//
// Get this instance of the Root Bridge.
@@ -1793,7 +1890,6 @@ RootBridgeIoConfiguration ( );
Descriptor = RootBridge->ConfigBuffer;
for (Index = TypeIo; Index < TypeMax; Index++) {
-
ResAllocNode = &RootBridge->ResAllocNode[Index];
if (ResAllocNode->Status != ResAllocated) {
@@ -1805,48 +1901,48 @@ RootBridgeIoConfiguration ( // According to UEFI 2.7, RootBridgeIo->Configuration should return address
// range in CPU view (host address), and ResAllocNode->Base is already a CPU
// view address (host address).
- Descriptor->AddrRangeMin = ResAllocNode->Base;
- Descriptor->AddrRangeMax = ResAllocNode->Base + ResAllocNode->Length - 1;
- Descriptor->AddrLen = ResAllocNode->Length;
+ Descriptor->AddrRangeMin = ResAllocNode->Base;
+ Descriptor->AddrRangeMax = ResAllocNode->Base + ResAllocNode->Length - 1;
+ Descriptor->AddrLen = ResAllocNode->Length;
Descriptor->AddrTranslationOffset = GetTranslationByResourceType (
- RootBridge,
- ResAllocNode->Type
- );
+ RootBridge,
+ ResAllocNode->Type
+ );
switch (ResAllocNode->Type) {
-
- case TypeIo:
- Descriptor->ResType = ACPI_ADDRESS_SPACE_TYPE_IO;
- break;
-
- case TypePMem32:
- Descriptor->SpecificFlag = EFI_ACPI_MEMORY_RESOURCE_SPECIFIC_FLAG_CACHEABLE_PREFETCHABLE;
- case TypeMem32:
- Descriptor->ResType = ACPI_ADDRESS_SPACE_TYPE_MEM;
- Descriptor->AddrSpaceGranularity = 32;
- break;
-
- case TypePMem64:
- Descriptor->SpecificFlag = EFI_ACPI_MEMORY_RESOURCE_SPECIFIC_FLAG_CACHEABLE_PREFETCHABLE;
- case TypeMem64:
- Descriptor->ResType = ACPI_ADDRESS_SPACE_TYPE_MEM;
- Descriptor->AddrSpaceGranularity = 64;
- break;
-
- case TypeBus:
- Descriptor->ResType = ACPI_ADDRESS_SPACE_TYPE_BUS;
- break;
-
- default:
- break;
+ case TypeIo:
+ Descriptor->ResType = ACPI_ADDRESS_SPACE_TYPE_IO;
+ break;
+
+ case TypePMem32:
+ Descriptor->SpecificFlag = EFI_ACPI_MEMORY_RESOURCE_SPECIFIC_FLAG_CACHEABLE_PREFETCHABLE;
+ case TypeMem32:
+ Descriptor->ResType = ACPI_ADDRESS_SPACE_TYPE_MEM;
+ Descriptor->AddrSpaceGranularity = 32;
+ break;
+
+ case TypePMem64:
+ Descriptor->SpecificFlag = EFI_ACPI_MEMORY_RESOURCE_SPECIFIC_FLAG_CACHEABLE_PREFETCHABLE;
+ case TypeMem64:
+ Descriptor->ResType = ACPI_ADDRESS_SPACE_TYPE_MEM;
+ Descriptor->AddrSpaceGranularity = 64;
+ break;
+
+ case TypeBus:
+ Descriptor->ResType = ACPI_ADDRESS_SPACE_TYPE_BUS;
+ break;
+
+ default:
+ break;
}
Descriptor++;
}
+
//
// Terminate the entries.
//
- End = (EFI_ACPI_END_TAG_DESCRIPTOR *) Descriptor;
+ End = (EFI_ACPI_END_TAG_DESCRIPTOR *)Descriptor;
End->Desc = ACPI_END_TAG_DESCRIPTOR;
End->Checksum = 0x0;
|