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| author | Tian Feng <feng.tian@intel.com> | 2015-06-09 03:21:32 +0000 |
|---|---|---|
| committer | erictian <erictian@Edk2> | 2015-06-09 03:21:32 +0000 |
| commit | d525ec10235c382581cd937fbb64d5d74c5dcbf7 (patch) | |
| tree | 52dde1ca72dd60a24a21c65e660fd89992b08d4d /MdeModulePkg/Bus/Pci/EhciDxe | |
| parent | 3ee12d880015bb96037e6db33d8b2d76ee4a49e1 (diff) | |
| download | edk2-d525ec10235c382581cd937fbb64d5d74c5dcbf7.zip edk2-d525ec10235c382581cd937fbb64d5d74c5dcbf7.tar.gz edk2-d525ec10235c382581cd937fbb64d5d74c5dcbf7.tar.bz2 | |
MdeModulePkg/EhciDxe: Update async polling interval to 1ms.
Updating the async polling interval from 50ms to 1ms for better performance.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Tian Feng <feng.tian@intel.com>
Reviewed-by: Star Zeng <star.zeng@intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@17586 6f19259b-4bc3-4df7-8a09-765794883524
Diffstat (limited to 'MdeModulePkg/Bus/Pci/EhciDxe')
| -rw-r--r-- | MdeModulePkg/Bus/Pci/EhciDxe/Ehci.h | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/MdeModulePkg/Bus/Pci/EhciDxe/Ehci.h b/MdeModulePkg/Bus/Pci/EhciDxe/Ehci.h index 4327f23..7177658 100644 --- a/MdeModulePkg/Bus/Pci/EhciDxe/Ehci.h +++ b/MdeModulePkg/Bus/Pci/EhciDxe/Ehci.h @@ -2,7 +2,7 @@ Provides some data struct used by EHCI controller driver.
-Copyright (c) 2006 - 2012, Intel Corporation. All rights reserved.<BR>
+Copyright (c) 2006 - 2015, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
@@ -66,10 +66,10 @@ typedef struct _USB2_HC_DEV USB2_HC_DEV; //
// Sync and Async transfer polling interval, set by experience,
-// and the unit of Async is 100us, means 50ms as interval.
+// and the unit of Async is 100us, means 1ms as interval.
//
#define EHC_SYNC_POLL_INTERVAL (1 * EHC_1_MILLISECOND)
-#define EHC_ASYNC_POLL_INTERVAL (50 * 10000U)
+#define EHC_ASYNC_POLL_INTERVAL EFI_TIMER_PERIOD_MILLISECONDS(1)
//
// EHCI debug port control status register bit definition
|