diff options
| author | Gao Cheng <gao.cheng@intel.com> | 2023-09-13 14:16:16 +0800 |
|---|---|---|
| committer | mergify[bot] <37929162+mergify[bot]@users.noreply.github.com> | 2023-09-28 02:02:11 +0000 |
| commit | f36e1ec1f0a5fd3be84913e09181d7813444b620 (patch) | |
| tree | 24796b01db861452c318df8ae25ce3ad85706272 /Maintainers.txt | |
| parent | ad1c0394b1770315099e511de7c88a04d7af76f2 (diff) | |
| download | edk2-f36e1ec1f0a5fd3be84913e09181d7813444b620.zip edk2-f36e1ec1f0a5fd3be84913e09181d7813444b620.tar.gz edk2-f36e1ec1f0a5fd3be84913e09181d7813444b620.tar.bz2 | |
MdeModulePkg/Xhci: Skip size round up for TRB during address translation
REF:https://bugzilla.tianocore.org/show_bug.cgi?id=4560
TRB Template is 16 bytes. When boundary checking is 64 bytes for xHCI
device/host memory address, it may exceed xHCI host memory pool and
cause unwanted DXE_ASSERT. Introduce a new input parameter to indicate
whether to enforce 64byte size alignment and round up. For TRB case,
should set it to FALSE to skip the size round up.
Signed-off-by: Gao Cheng <gao.cheng@intel.com>
Cc: Hao A Wu <hao.a.wu@intel.com>
Cc: Ray Ni <ray.ni@intel.com>
Cc: Jian J Wang <jian.j.wang@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Reviewed-by: Hao A Wu <hao.a.wu@intel.com>
Diffstat (limited to 'Maintainers.txt')
0 files changed, 0 insertions, 0 deletions