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| author | Chasel Chiu <chasel.chiu@intel.com> | 2022-07-18 21:08:31 -0700 |
|---|---|---|
| committer | mergify[bot] <37929162+mergify[bot]@users.noreply.github.com> | 2022-07-19 22:24:31 +0000 |
| commit | 24eac4caf31afae48349af44588a52783c1819b8 (patch) | |
| tree | 7fb5df8425fe503e48714bfeb1eba2758401a2e9 /IntelFsp2WrapperPkg/FspsWrapperPeim | |
| parent | 140446cd595cad870a0e8cef7a367bae8f09effa (diff) | |
| download | edk2-24eac4caf31afae48349af44588a52783c1819b8.zip edk2-24eac4caf31afae48349af44588a52783c1819b8.tar.gz edk2-24eac4caf31afae48349af44588a52783c1819b8.tar.bz2 | |
IntelFsp2WrapperPkg: Support 64bit FspResetType for X64 build.
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3999
FspResetType will be either 32bit or 64 bit basing on
the build type.
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Cc: Star Zeng <star.zeng@intel.com>
Signed-off-by: Chasel Chiu <chasel.chiu@intel.com>
Reviewed-by: Nate DeSimone <nathaniel.l.desimone@intel.com>
Diffstat (limited to 'IntelFsp2WrapperPkg/FspsWrapperPeim')
| -rw-r--r-- | IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.c | 15 |
1 files changed, 7 insertions, 8 deletions
diff --git a/IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.c b/IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.c index fadadd4..ee48dd6 100644 --- a/IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.c +++ b/IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.c @@ -96,7 +96,7 @@ S3EndOfPeiNotify ( //
if ((Status >= FSP_STATUS_RESET_REQUIRED_COLD) && (Status <= FSP_STATUS_RESET_REQUIRED_8)) {
DEBUG ((DEBUG_INFO, "FSP S3NotifyPhase AfterPciEnumeration requested reset 0x%x\n", Status));
- CallFspWrapperResetSystem ((UINT32)Status);
+ CallFspWrapperResetSystem (Status);
}
NotifyPhaseParams.Phase = EnumInitPhaseReadyToBoot;
@@ -108,7 +108,7 @@ S3EndOfPeiNotify ( //
if ((Status >= FSP_STATUS_RESET_REQUIRED_COLD) && (Status <= FSP_STATUS_RESET_REQUIRED_8)) {
DEBUG ((DEBUG_INFO, "FSP S3NotifyPhase ReadyToBoot requested reset 0x%x\n", Status));
- CallFspWrapperResetSystem ((UINT32)Status);
+ CallFspWrapperResetSystem (Status);
}
NotifyPhaseParams.Phase = EnumInitPhaseEndOfFirmware;
@@ -120,7 +120,7 @@ S3EndOfPeiNotify ( //
if ((Status >= FSP_STATUS_RESET_REQUIRED_COLD) && (Status <= FSP_STATUS_RESET_REQUIRED_8)) {
DEBUG ((DEBUG_INFO, "FSP S3NotifyPhase EndOfFirmware requested reset 0x%x\n", Status));
- CallFspWrapperResetSystem ((UINT32)Status);
+ CallFspWrapperResetSystem (Status);
}
return EFI_SUCCESS;
@@ -186,16 +186,15 @@ FspSiliconInitDoneGetFspHobList ( @return FSP-S UPD Data Address
**/
-
UINTN
GetFspsUpdDataAddress (
VOID
)
{
if (PcdGet64 (PcdFspsUpdDataAddress64) != 0) {
- return (UINTN) PcdGet64 (PcdFspsUpdDataAddress64);
+ return (UINTN)PcdGet64 (PcdFspsUpdDataAddress64);
} else {
- return (UINTN) PcdGet32 (PcdFspsUpdDataAddress);
+ return (UINTN)PcdGet32 (PcdFspsUpdDataAddress);
}
}
@@ -310,7 +309,7 @@ PeiMemoryDiscoveredNotify ( SourceData = (UINTN *)((UINTN)FspsHeaderPtr->ImageBase + (UINTN)FspsHeaderPtr->CfgRegionOffset);
CopyMem (FspsUpdDataPtr, SourceData, (UINTN)FspsHeaderPtr->CfgRegionSize);
} else {
- FspsUpdDataPtr = (FSPS_UPD_COMMON *) GetFspsUpdDataAddress();
+ FspsUpdDataPtr = (FSPS_UPD_COMMON *)GetFspsUpdDataAddress ();
ASSERT (FspsUpdDataPtr != NULL);
}
@@ -327,7 +326,7 @@ PeiMemoryDiscoveredNotify ( //
if ((Status >= FSP_STATUS_RESET_REQUIRED_COLD) && (Status <= FSP_STATUS_RESET_REQUIRED_8)) {
DEBUG ((DEBUG_INFO, "FspSiliconInitApi requested reset 0x%x\n", Status));
- CallFspWrapperResetSystem ((UINT32)Status);
+ CallFspWrapperResetSystem (Status);
}
if (EFI_ERROR (Status)) {
|