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| author | Chasel, Chiu <chasel.chiu@intel.com> | 2018-11-06 15:31:31 +0800 |
|---|---|---|
| committer | Chasel, Chiu <chasel.chiu@intel.com> | 2018-11-20 12:03:52 +0800 |
| commit | 115336ccaf0635c659996bc41a47914f9d837275 (patch) | |
| tree | 14c87c3554826ea44725cf98c1de86762763f0e6 /IntelFsp2WrapperPkg/FspsWrapperPeim | |
| parent | de1e1195b34aad43fc85cdebf6d5b0b213eaa3d0 (diff) | |
| download | edk2-115336ccaf0635c659996bc41a47914f9d837275.zip edk2-115336ccaf0635c659996bc41a47914f9d837275.tar.gz edk2-115336ccaf0635c659996bc41a47914f9d837275.tar.bz2 | |
IntelFsp2WrapperPkg: Support FSP Dispatch mode
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1300
Provides PCD selection for FSP Wrapper to support Dispatch
mode. Also PcdFspmBaseAddress should support Dynamic for
recovery scenario (multiple FSP-M binary in flash)
Test: Verified on internal platform and both API and
DISPATCH modes booted successfully.
Cc: Jiewen Yao <Jiewen.yao@intel.com>
Cc: Desimone Nathaniel L <nathaniel.l.desimone@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Chasel Chiu <chasel.chiu@intel.com>
Reviewed-by: Jiewen Yao <Jiewen.yao@intel.com>
Diffstat (limited to 'IntelFsp2WrapperPkg/FspsWrapperPeim')
| -rw-r--r-- | IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.c | 14 | ||||
| -rw-r--r-- | IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.inf | 3 |
2 files changed, 14 insertions, 3 deletions
diff --git a/IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.c b/IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.c index 70dac7a..69cf568 100644 --- a/IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.c +++ b/IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.c @@ -3,7 +3,7 @@ register TemporaryRamDonePpi to call TempRamExit API, and register MemoryDiscoveredPpi
notify to call FspSiliconInit API.
- Copyright (c) 2014 - 2017, Intel Corporation. All rights reserved.<BR>
+ Copyright (c) 2014 - 2018, Intel Corporation. All rights reserved.<BR> This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
@@ -349,7 +349,17 @@ FspsWrapperPeimEntryPoint ( {
DEBUG ((DEBUG_INFO, "FspsWrapperPeimEntryPoint\n"));
- FspsWrapperInit ();
+ if (FixedPcdGet8 (PcdFspModeSelection) == 1) { + FspsWrapperInit (); + } else { + PeiServicesInstallFvInfoPpi ( + NULL, + (VOID *)(UINTN) PcdGet32 (PcdFspsBaseAddress), + (UINT32)((EFI_FIRMWARE_VOLUME_HEADER *) (UINTN) PcdGet32 (PcdFspsBaseAddress))->FvLength, + NULL, + NULL + ); + } return EFI_SUCCESS;
}
diff --git a/IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.inf b/IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.inf index cd87a99..1e63f40 100644 --- a/IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.inf +++ b/IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.inf @@ -6,7 +6,7 @@ # register TemporaryRamDonePpi to call TempRamExit API, and register MemoryDiscoveredPpi
# notify to call FspSiliconInit API.
#
-# Copyright (c) 2014 - 2017, Intel Corporation. All rights reserved.<BR>
+# Copyright (c) 2014 - 2018, Intel Corporation. All rights reserved.<BR> #
# This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
@@ -68,6 +68,7 @@ [Pcd]
gIntelFsp2WrapperTokenSpaceGuid.PcdFspsBaseAddress ## CONSUMES
gIntelFsp2WrapperTokenSpaceGuid.PcdFspsUpdDataAddress ## CONSUMES
+ gIntelFsp2WrapperTokenSpaceGuid.PcdFspModeSelection ## CONSUMES [Guids]
gFspHobGuid ## CONSUMES ## HOB
|