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| author | Jiewen Yao <jiewen.yao@intel.com> | 2016-06-17 10:38:09 +0800 |
|---|---|---|
| committer | Jiewen Yao <jiewen.yao@intel.com> | 2016-06-18 07:17:04 +0800 |
| commit | f862a3b6f9dc026ea0e108fd548c65c75346bada (patch) | |
| tree | e4bea06d7085e1ef497ae93c8b6518d5359a8dc5 /IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.c | |
| parent | e918029fbce507f7de5b99112582fd41993e58c5 (diff) | |
| download | edk2-f862a3b6f9dc026ea0e108fd548c65c75346bada.zip edk2-f862a3b6f9dc026ea0e108fd548c65c75346bada.tar.gz edk2-f862a3b6f9dc026ea0e108fd548c65c75346bada.tar.bz2 | |
IntelFsp2WrapperPkg: Add support to handle ResetRequired return Status from FSP.
As per FSP 2.0 spec, FSP shall not trigger system reset and instead it
shall return from the FSP API to the BL/Wrapper with the required reset
type. The changes are to handle the ResetRequired return code from FSP
APIs and provide lib interface for platform to trigger the actual reset.
Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Cc: Amy Chan <amy.chan@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Satya Yarlagadda <satya.p.yarlagadda@intel.com>
Signed-off-by: Jiewen Yao <jiewen.yao@intel.com>
Reviewed-by: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Diffstat (limited to 'IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.c')
| -rw-r--r-- | IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.c | 33 |
1 files changed, 33 insertions, 0 deletions
diff --git a/IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.c b/IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.c index 9bc720f..7a65ad7 100644 --- a/IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.c +++ b/IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.c @@ -94,14 +94,38 @@ S3EndOfPeiNotify( Status = CallFspNotifyPhase (&NotifyPhaseParams);
DEBUG((DEBUG_INFO, "FSP S3NotifyPhase AfterPciEnumeration status: 0x%x\n", Status));
+ //
+ // Reset the system if FSP API returned FSP_STATUS_RESET_REQUIRED status
+ //
+ if ((Status >= FSP_STATUS_RESET_REQUIRED_COLD) && (Status <= FSP_STATUS_RESET_REQUIRED_8)) {
+ DEBUG((DEBUG_INFO, "FSP S3NotifyPhase AfterPciEnumeration requested reset 0x%x\n", Status));
+ CallFspWrapperResetSystem ((UINT32)Status);
+ }
+
NotifyPhaseParams.Phase = EnumInitPhaseReadyToBoot;
Status = CallFspNotifyPhase (&NotifyPhaseParams);
DEBUG((DEBUG_INFO, "FSP S3NotifyPhase ReadyToBoot status: 0x%x\n", Status));
+ //
+ // Reset the system if FSP API returned FSP_STATUS_RESET_REQUIRED status
+ //
+ if ((Status >= FSP_STATUS_RESET_REQUIRED_COLD) && (Status <= FSP_STATUS_RESET_REQUIRED_8)) {
+ DEBUG((DEBUG_INFO, "FSP S3NotifyPhase ReadyToBoot requested reset 0x%x\n", Status));
+ CallFspWrapperResetSystem ((UINT32)Status);
+ }
+
NotifyPhaseParams.Phase = EnumInitPhaseEndOfFirmware;
Status = CallFspNotifyPhase (&NotifyPhaseParams);
DEBUG((DEBUG_INFO, "FSP S3NotifyPhase EndOfFirmware status: 0x%x\n", Status));
+ //
+ // Reset the system if FSP API returned FSP_STATUS_RESET_REQUIRED status
+ //
+ if ((Status >= FSP_STATUS_RESET_REQUIRED_COLD) && (Status <= FSP_STATUS_RESET_REQUIRED_8)) {
+ DEBUG((DEBUG_INFO, "FSP S3NotifyPhase EndOfFirmware requested reset 0x%x\n", Status));
+ CallFspWrapperResetSystem ((UINT32)Status);
+ }
+
return EFI_SUCCESS;
}
@@ -229,6 +253,15 @@ PeiMemoryDiscoveredNotify ( Status = CallFspSiliconInit ((VOID *)FspsUpdDataPtr);
PERF_END_EX(&gFspApiPerformanceGuid, "EventRec", NULL, 0, 0x907F);
DEBUG ((DEBUG_INFO, "Total time spent executing FspSiliconInitApi: %d millisecond\n", DivU64x32 (GetTimeInNanoSecond (AsmReadTsc () - TimeStampCounterStart), 1000000)));
+
+ //
+ // Reset the system if FSP API returned FSP_STATUS_RESET_REQUIRED status
+ //
+ if ((Status >= FSP_STATUS_RESET_REQUIRED_COLD) && (Status <= FSP_STATUS_RESET_REQUIRED_8)) {
+ DEBUG((DEBUG_INFO, "FspSiliconInitApi requested reset 0x%x\n", Status));
+ CallFspWrapperResetSystem ((UINT32)Status);
+ }
+
if (EFI_ERROR(Status)) {
DEBUG ((DEBUG_ERROR, "ERROR - Failed to execute FspSiliconInitApi(), Status = %r\n", Status));
}
|