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author | Antoine Cœur <coeur@gmx.fr> | 2019-07-09 17:10:11 +0800 |
---|---|---|
committer | Chasel Chiu <chasel.chiu@intel.com> | 2019-07-09 21:40:00 +0800 |
commit | f527942e6bdd9f198db90f2de99a0482e9be5b1b (patch) | |
tree | 0efa7e71a17fd203774a2b02630ca1b09c0a6683 /IntelFsp2Pkg/FspSecCore | |
parent | 8a842b31b93323ee3dc7631059292d30f6179cd3 (diff) | |
download | edk2-f527942e6bdd9f198db90f2de99a0482e9be5b1b.zip edk2-f527942e6bdd9f198db90f2de99a0482e9be5b1b.tar.gz edk2-f527942e6bdd9f198db90f2de99a0482e9be5b1b.tar.bz2 |
FmpDevicePkg: Fix various typos
Fix one typo in FmpDevicePkg.
Signed-off-by: Cœur <coeur@gmx.fr>
Reviewed-by: Star Zeng <star.zeng@intel.com>
Reviewed-by: Chasel Chiu <chasel.chiu@intel.com>
Diffstat (limited to 'IntelFsp2Pkg/FspSecCore')
-rw-r--r-- | IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryM.nasm | 4 | ||||
-rw-r--r-- | IntelFsp2Pkg/FspSecCore/Ia32/InitializeFpu.nasm | 4 | ||||
-rw-r--r-- | IntelFsp2Pkg/FspSecCore/Ia32/SaveRestoreSseNasm.inc | 4 | ||||
-rw-r--r-- | IntelFsp2Pkg/FspSecCore/Ia32/Stack.nasm | 4 | ||||
-rw-r--r-- | IntelFsp2Pkg/FspSecCore/SecFsp.c | 4 | ||||
-rw-r--r-- | IntelFsp2Pkg/FspSecCore/SecMain.c | 2 | ||||
-rw-r--r-- | IntelFsp2Pkg/FspSecCore/Vtf0/Ia16/ResetVec.asm16 | 4 |
7 files changed, 13 insertions, 13 deletions
diff --git a/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryM.nasm b/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryM.nasm index f14c18c..e7261b4 100644 --- a/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryM.nasm +++ b/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryM.nasm @@ -194,9 +194,9 @@ StackSetupDone: ;
; Pass BFV into the PEI Core
- ; It uses relative address to calucate the actual boot FV base
+ ; It uses relative address to calculate the actual boot FV base
; For FSP implementation with single FV, PcdFspBootFirmwareVolumeBase and
- ; PcdFspAreaBaseAddress are the same. For FSP with mulitple FVs,
+ ; PcdFspAreaBaseAddress are the same. For FSP with multiple FVs,
; they are different. The code below can handle both cases.
;
call ASM_PFX(AsmGetFspBaseAddress)
diff --git a/IntelFsp2Pkg/FspSecCore/Ia32/InitializeFpu.nasm b/IntelFsp2Pkg/FspSecCore/Ia32/InitializeFpu.nasm index e1886ea..ebc91c4 100644 --- a/IntelFsp2Pkg/FspSecCore/Ia32/InitializeFpu.nasm +++ b/IntelFsp2Pkg/FspSecCore/Ia32/InitializeFpu.nasm @@ -1,6 +1,6 @@ ;------------------------------------------------------------------------------
;
-; Copyright (c) 2015, Intel Corporation. All rights reserved.<BR>
+; Copyright (c) 2015 - 2019, Intel Corporation. All rights reserved.<BR>
; SPDX-License-Identifier: BSD-2-Clause-Patent
;
; Abstract:
@@ -46,7 +46,7 @@ ASM_PFX(InitializeFloatingPointUnits): fldcw [ASM_PFX(mFpuControlWord)]
;
- ; Use CpuId instructuion (CPUID.01H:EDX.SSE[bit 25] = 1) to test
+ ; Use CpuId instruction (CPUID.01H:EDX.SSE[bit 25] = 1) to test
; whether the processor supports SSE instruction.
;
mov eax, 1
diff --git a/IntelFsp2Pkg/FspSecCore/Ia32/SaveRestoreSseNasm.inc b/IntelFsp2Pkg/FspSecCore/Ia32/SaveRestoreSseNasm.inc index b257deb..4c321cb 100644 --- a/IntelFsp2Pkg/FspSecCore/Ia32/SaveRestoreSseNasm.inc +++ b/IntelFsp2Pkg/FspSecCore/Ia32/SaveRestoreSseNasm.inc @@ -1,6 +1,6 @@ ;------------------------------------------------------------------------------
;
-; Copyright (c) 2015, Intel Corporation. All rights reserved.<BR>
+; Copyright (c) 2015 - 2019, Intel Corporation. All rights reserved.<BR>
; SPDX-License-Identifier: BSD-2-Clause-Patent
;
; Abstract:
@@ -150,7 +150,7 @@ NextAddress: fldcw [FpuControlWord]
;
- ; Use CpuId instructuion (CPUID.01H:EDX.SSE[bit 25] = 1) to test
+ ; Use CpuId instruction (CPUID.01H:EDX.SSE[bit 25] = 1) to test
; whether the processor supports SSE instruction.
;
mov eax, 1
diff --git a/IntelFsp2Pkg/FspSecCore/Ia32/Stack.nasm b/IntelFsp2Pkg/FspSecCore/Ia32/Stack.nasm index d72212e..5a7e27c 100644 --- a/IntelFsp2Pkg/FspSecCore/Ia32/Stack.nasm +++ b/IntelFsp2Pkg/FspSecCore/Ia32/Stack.nasm @@ -1,6 +1,6 @@ ;------------------------------------------------------------------------------
;
-; Copyright (c) 2015, Intel Corporation. All rights reserved.<BR>
+; Copyright (c) 2015 - 2019, Intel Corporation. All rights reserved.<BR>
; SPDX-License-Identifier: BSD-2-Clause-Patent
;
; Abstract:
@@ -58,7 +58,7 @@ ASM_PFX(SecSwitchStack): mov esp, eax ; From now, esp is pointed to permanent memory
;
- ; Fixup the ebp point to permenent memory
+ ; Fixup the ebp point to permanent memory
;
mov eax, ebp
sub eax, ebx
diff --git a/IntelFsp2Pkg/FspSecCore/SecFsp.c b/IntelFsp2Pkg/FspSecCore/SecFsp.c index 6497c88..446d173 100644 --- a/IntelFsp2Pkg/FspSecCore/SecFsp.c +++ b/IntelFsp2Pkg/FspSecCore/SecFsp.c @@ -1,6 +1,6 @@ /** @file
- Copyright (c) 2014 - 2018, Intel Corporation. All rights reserved.<BR>
+ Copyright (c) 2014 - 2019, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
@@ -169,7 +169,7 @@ FspGlobalDataInit ( SerialPortInitialize ();
//
- // Ensure the golbal data pointer is valid
+ // Ensure the global data pointer is valid
//
ASSERT (GetFspGlobalDataPointer () == PeiFspData);
diff --git a/IntelFsp2Pkg/FspSecCore/SecMain.c b/IntelFsp2Pkg/FspSecCore/SecMain.c index cd3ab46..a63d133 100644 --- a/IntelFsp2Pkg/FspSecCore/SecMain.c +++ b/IntelFsp2Pkg/FspSecCore/SecMain.c @@ -110,7 +110,7 @@ SecStartup ( // |-------------------|---->
// | |
// | |
- // | Heap | PeiTemporayRamSize
+ // | Heap | PeiTemporaryRamSize
// | |
// | |
// |-------------------|----> TempRamBase
diff --git a/IntelFsp2Pkg/FspSecCore/Vtf0/Ia16/ResetVec.asm16 b/IntelFsp2Pkg/FspSecCore/Vtf0/Ia16/ResetVec.asm16 index f25de02..c519874 100644 --- a/IntelFsp2Pkg/FspSecCore/Vtf0/Ia16/ResetVec.asm16 +++ b/IntelFsp2Pkg/FspSecCore/Vtf0/Ia16/ResetVec.asm16 @@ -2,7 +2,7 @@ ; Reset Vector Data structure
; This structure is located at 0xFFFFFFC0
;
-; Copyright (c) 2014, Intel Corporation. All rights reserved.<BR>
+; Copyright (c) 2014 - 2019, Intel Corporation. All rights reserved.<BR>
; SPDX-License-Identifier: BSD-2-Clause-Patent
;
;;
@@ -61,7 +61,7 @@ ApStartup: ;
; Jmp Rel16 instruction
; Use machine code directly in case of the assembler optimization
- ; SEC entry point relatvie address will be fixed up by some build tool.
+ ; SEC entry point relative address will be fixed up by some build tool.
;
; Typically, SEC entry point is the function _ModuleEntryPoint() defined in
; SecEntry.asm
|