IntelFsp2Pkg/FspSecCore: Add FSP-I API for SMM support.

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3993
Add FSP-I API entry point for SMM support.
Also update 64bit API entry code to assign ApiIdx to RAX
to avoid confusion.

Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Cc: Star Zeng <star.zeng@intel.com>
Signed-off-by: Chasel Chiu <chasel.chiu@intel.com>
Signed-off-by: Hongbin1 Zhang <hongbin1.zhang@intel.com>
Reviewed-by: Nate DeSimone <nathaniel.l.desimone@intel.com>

7 files changed, 163 insertions, 8 deletions

diff --git a/IntelFsp2Pkg/FspSecCore/FspSecCoreI.inf b/IntelFsp2Pkg/FspSecCore/FspSecCoreI.inf
new file mode 100644
index 0000000..d31576c
--- /dev/null
+++ b/IntelFsp2Pkg/FspSecCore/FspSecCoreI.inf
@@ -0,0 +1,54 @@
+## @file

+#  Sec Core for FSP

+#

+#  Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>

+#

+#  SPDX-License-Identifier: BSD-2-Clause-Patent

+#

+##

+

+[Defines]

+  INF_VERSION                    = 0x00010005

+  BASE_NAME                      = FspSecCoreI

+  FILE_GUID                      = 558782b5-782d-415e-ab9e-0ceb79dc3425

+  MODULE_TYPE                    = SEC

+  VERSION_STRING                 = 1.0

+

+#

+# The following information is for reference only and not required by the build tools.

+#

+#  VALID_ARCHITECTURES           = IA32 X64

+#

+

+[Sources]

+  SecFspApiChk.c

+  SecFsp.h

+

+[Sources.X64]

+  X64/FspApiEntryI.nasm

+  X64/FspApiEntryCommon.nasm

+  X64/FspHelper.nasm

+

+[Sources.IA32]

+  Ia32/FspApiEntryI.nasm

+  Ia32/FspApiEntryCommon.nasm

+  Ia32/FspHelper.nasm

+

+[Binaries.Ia32]

+  RAW|Vtf0/Bin/ResetVec.ia32.raw |GCC

+

+[Packages]

+  MdePkg/MdePkg.dec

+  IntelFsp2Pkg/IntelFsp2Pkg.dec

+

+[LibraryClasses]

+  BaseMemoryLib

+  DebugLib

+  BaseLib

+  PciCf8Lib

+  SerialPortLib

+  FspSwitchStackLib

+  FspCommonLib

+  FspSecPlatformLib

+

+

diff --git a/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryI.nasm b/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryI.nasm
new file mode 100644
index 0000000..e9365d6
--- /dev/null
+++ b/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryI.nasm
@@ -0,0 +1,44 @@
+;; @file

+;  Provide FSP API entry points.

+;

+; Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>

+; SPDX-License-Identifier: BSD-2-Clause-Patent

+;;

+

+    SECTION .text

+

+;

+; Following functions will be provided in C

+;

+extern ASM_PFX(FspApiCommon)

+

+;----------------------------------------------------------------------------

+; FspApiCommonContinue API

+;

+; This is the FSP API common entry point to resume the FSP execution

+;

+;----------------------------------------------------------------------------

+global ASM_PFX(FspApiCommonContinue)

+ASM_PFX(FspApiCommonContinue):

+  jmp $

+

+;----------------------------------------------------------------------------

+; FspSmmInit API

+;

+; This FSP API will notify the FSP about the different phases in the boot

+; process

+;

+;----------------------------------------------------------------------------

+global ASM_PFX(FspSmmInitApi)

+ASM_PFX(FspSmmInitApi):

+  mov    eax,  7 ; FSP_API_INDEX.FspSmmInitApiIndex

+  jmp    ASM_PFX(FspApiCommon)

+

+;----------------------------------------------------------------------------

+; Module Entrypoint API

+;----------------------------------------------------------------------------

+global ASM_PFX(_ModuleEntryPoint)

+ASM_PFX(_ModuleEntryPoint):

+  jmp  $

+  ; Add reference to APIs so that it will not be optimized by compiler

+  jmp  ASM_PFX(FspSmmInitApi)

diff --git a/IntelFsp2Pkg/FspSecCore/SecFspApiChk.c b/IntelFsp2Pkg/FspSecCore/SecFspApiChk.c
index e22a88c..35d223a 100644
--- a/IntelFsp2Pkg/FspSecCore/SecFspApiChk.c
+++ b/IntelFsp2Pkg/FspSecCore/SecFspApiChk.c
@@ -71,6 +71,19 @@ FspApiCallingCheck (
         Status = EFI_INVALID_PARAMETER;

       }

     }

+  } else if (ApiIdx == FspSmmInitApiIndex) {

+    //

+    // FspSmmInitApiIndex check

+    //

+    if ((FspData == NULL) || ((UINTN)FspData == MAX_ADDRESS) || ((UINTN)FspData == MAX_UINT32)) {

+      Status = EFI_UNSUPPORTED;

+    } else {

+      if (FspData->Signature != FSP_GLOBAL_DATA_SIGNATURE) {

+        Status = EFI_UNSUPPORTED;

+      } else if (EFI_ERROR (FspUpdSignatureCheck (FspSmmInitApiIndex, ApiParam))) {

+        Status = EFI_INVALID_PARAMETER;

+      }

+    }

   } else {

     Status = EFI_UNSUPPORTED;

   }

diff --git a/IntelFsp2Pkg/FspSecCore/X64/Fsp22ApiEntryS.nasm b/IntelFsp2Pkg/FspSecCore/X64/Fsp22ApiEntryS.nasm
index c739793..4202925 100644
--- a/IntelFsp2Pkg/FspSecCore/X64/Fsp22ApiEntryS.nasm
+++ b/IntelFsp2Pkg/FspSecCore/X64/Fsp22ApiEntryS.nasm
@@ -24,7 +24,7 @@ STACK_SAVED_RAX_OFFSET       EQU   8 * 7 ; size of a general purpose register *
 ;----------------------------------------------------------------------------

 global ASM_PFX(NotifyPhaseApi)

 ASM_PFX(NotifyPhaseApi):

-  mov    eax,  2 ; FSP_API_INDEX.NotifyPhaseApiIndex

+  mov    rax,  2 ; FSP_API_INDEX.NotifyPhaseApiIndex

   jmp    ASM_PFX(FspApiCommon)

 

 ;----------------------------------------------------------------------------

@@ -36,7 +36,7 @@ ASM_PFX(NotifyPhaseApi):
 ;----------------------------------------------------------------------------

 global ASM_PFX(FspSiliconInitApi)

 ASM_PFX(FspSiliconInitApi):

-  mov    eax,  5 ; FSP_API_INDEX.FspSiliconInitApiIndex

+  mov    rax,  5 ; FSP_API_INDEX.FspSiliconInitApiIndex

   jmp    ASM_PFX(FspApiCommon)

 

 ;----------------------------------------------------------------------------

@@ -54,7 +54,7 @@ ASM_PFX(FspSiliconInitApi):
 

 global ASM_PFX(FspMultiPhaseSiInitApi)

 ASM_PFX(FspMultiPhaseSiInitApi):

-  mov    eax,  6 ; FSP_API_INDEX.FspMultiPhaseSiInitApiIndex

+  mov    rax,  6 ; FSP_API_INDEX.FspMultiPhaseSiInitApiIndex

   jmp    ASM_PFX(FspApiCommon)

 

 ;----------------------------------------------------------------------------

@@ -68,7 +68,7 @@ ASM_PFX(FspApiCommonContinue):
   ;

   ; Handle FspMultiPhaseSiInitApiIndex API

   ;

-  cmp    eax, 6

+  cmp    rax, 6 ; FSP_API_INDEX.FspMultiPhaseSiInitApiIndex

   jnz    NotMultiPhaseSiInitApi

 

   PUSHA_64

diff --git a/IntelFsp2Pkg/FspSecCore/X64/FspApiEntryI.nasm b/IntelFsp2Pkg/FspSecCore/X64/FspApiEntryI.nasm
new file mode 100644
index 0000000..e74bf0a
--- /dev/null
+++ b/IntelFsp2Pkg/FspSecCore/X64/FspApiEntryI.nasm
@@ -0,0 +1,44 @@
+;; @file

+;  Provide FSP API entry points.

+;

+; Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>

+; SPDX-License-Identifier: BSD-2-Clause-Patent

+;;

+

+    SECTION .text

+

+;

+; Following functions will be provided in C

+;

+extern ASM_PFX(FspApiCommon)

+

+;----------------------------------------------------------------------------

+; FspApiCommonContinue API

+;

+; This is the FSP API common entry point to resume the FSP execution

+;

+;----------------------------------------------------------------------------

+global ASM_PFX(FspApiCommonContinue)

+ASM_PFX(FspApiCommonContinue):

+  jmp $

+

+;----------------------------------------------------------------------------

+; FspSmmInit API

+;

+; This FSP API will notify the FSP about the different phases in the boot

+; process

+;

+;----------------------------------------------------------------------------

+global ASM_PFX(FspSmmInitApi)

+ASM_PFX(FspSmmInitApi):

+  mov    rax,  7 ; FSP_API_INDEX.FspSmmInitApiIndex

+  jmp    ASM_PFX(FspApiCommon)

+

+;----------------------------------------------------------------------------

+; Module Entrypoint API

+;----------------------------------------------------------------------------

+global ASM_PFX(_ModuleEntryPoint)

+ASM_PFX(_ModuleEntryPoint):

+  jmp  $

+  ; Add reference to APIs so that it will not be optimized by compiler

+  jmp  ASM_PFX(FspSmmInitApi)

diff --git a/IntelFsp2Pkg/FspSecCore/X64/FspApiEntryM.nasm b/IntelFsp2Pkg/FspSecCore/X64/FspApiEntryM.nasm
index 4d965e1..dacf515 100644
--- a/IntelFsp2Pkg/FspSecCore/X64/FspApiEntryM.nasm
+++ b/IntelFsp2Pkg/FspSecCore/X64/FspApiEntryM.nasm
@@ -55,7 +55,7 @@ FSP_HEADER_CFGREG_OFFSET     EQU   24h
 ;----------------------------------------------------------------------------

 global ASM_PFX(FspMemoryInitApi)

 ASM_PFX(FspMemoryInitApi):

-  mov    eax,  3 ; FSP_API_INDEX.FspMemoryInitApiIndex

+  mov    rax,  3 ; FSP_API_INDEX.FspMemoryInitApiIndex

   jmp    ASM_PFX(FspApiCommon)

 

 ;----------------------------------------------------------------------------

@@ -66,7 +66,7 @@ ASM_PFX(FspMemoryInitApi):
 ;----------------------------------------------------------------------------

 global ASM_PFX(TempRamExitApi)

 ASM_PFX(TempRamExitApi):

-  mov    eax,  4 ; FSP_API_INDEX.TempRamExitApiIndex

+  mov    rax,  4 ; FSP_API_INDEX.TempRamExitApiIndex

   jmp    ASM_PFX(FspApiCommon)

 

 ;----------------------------------------------------------------------------

diff --git a/IntelFsp2Pkg/FspSecCore/X64/FspApiEntryS.nasm b/IntelFsp2Pkg/FspSecCore/X64/FspApiEntryS.nasm
index f863ef0..7e211fb 100644
--- a/IntelFsp2Pkg/FspSecCore/X64/FspApiEntryS.nasm
+++ b/IntelFsp2Pkg/FspSecCore/X64/FspApiEntryS.nasm
@@ -21,7 +21,7 @@ extern ASM_PFX(FspApiCommon)
 ;----------------------------------------------------------------------------

 global ASM_PFX(NotifyPhaseApi)

 ASM_PFX(NotifyPhaseApi):

-  mov    eax,  2 ; FSP_API_INDEX.NotifyPhaseApiIndex

+  mov    rax,  2 ; FSP_API_INDEX.NotifyPhaseApiIndex

   jmp    ASM_PFX(FspApiCommon)

 

 ;----------------------------------------------------------------------------

@@ -33,7 +33,7 @@ ASM_PFX(NotifyPhaseApi):
 ;----------------------------------------------------------------------------

 global ASM_PFX(FspSiliconInitApi)

 ASM_PFX(FspSiliconInitApi):

-  mov    eax,  5 ; FSP_API_INDEX.FspSiliconInitApiIndex

+  mov    rax,  5 ; FSP_API_INDEX.FspSiliconInitApiIndex

   jmp    ASM_PFX(FspApiCommon)

 

 ;----------------------------------------------------------------------------