diff options
| author | Ted Kuo <ted.kuo@intel.com> | 2022-04-15 01:37:39 -0700 |
|---|---|---|
| committer | mergify[bot] <37929162+mergify[bot]@users.noreply.github.com> | 2022-04-16 00:18:14 +0000 |
| commit | 00aa71ce20472f0a7bc01e735a0c419adf727def (patch) | |
| tree | a0b26a7b9be95b42b9f73c6e456893b760123c58 /IntelFsp2Pkg/FspSecCore/X64/FspApiEntryCommon.nasm | |
| parent | d40965b9877135028673884abc8f5a9b6b0ef5dc (diff) | |
| download | edk2-00aa71ce20472f0a7bc01e735a0c419adf727def.zip edk2-00aa71ce20472f0a7bc01e735a0c419adf727def.tar.gz edk2-00aa71ce20472f0a7bc01e735a0c419adf727def.tar.bz2 | |
IntelFsp2Pkg: FspSecCore support for X64
REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3893
1.Added FspSecCore support for X64.
2.Bumped FSP header revision to 7 to indicate FSP 64bit is supported.
3.Corrected few typos.
Cc: Chasel Chiu <chasel.chiu@intel.com>
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Cc: Star Zeng <star.zeng@intel.com>
Cc: Ashraf Ali S <ashraf.ali.s@intel.com>
Signed-off-by: Ted Kuo <ted.kuo@intel.com>
Reviewed-by: Chasel Chiu <chasel.chiu@intel.com>
Reviewed-by: Nate DeSimone <nathaniel.l.desimone@intel.com>
Diffstat (limited to 'IntelFsp2Pkg/FspSecCore/X64/FspApiEntryCommon.nasm')
| -rw-r--r-- | IntelFsp2Pkg/FspSecCore/X64/FspApiEntryCommon.nasm | 76 |
1 files changed, 76 insertions, 0 deletions
diff --git a/IntelFsp2Pkg/FspSecCore/X64/FspApiEntryCommon.nasm b/IntelFsp2Pkg/FspSecCore/X64/FspApiEntryCommon.nasm new file mode 100644 index 0000000..718e672 --- /dev/null +++ b/IntelFsp2Pkg/FspSecCore/X64/FspApiEntryCommon.nasm @@ -0,0 +1,76 @@ +;; @file
+; Provide FSP API entry points.
+;
+; Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;;
+
+ SECTION .text
+
+%include "PushPopRegsNasm.inc"
+
+STACK_SAVED_RAX_OFFSET EQU 8 * 7 ; size of a general purpose register * rax index
+
+;
+; Following functions will be provided in C
+;
+extern ASM_PFX(Loader2PeiSwitchStack)
+extern ASM_PFX(FspApiCallingCheck)
+
+;
+; Following functions will be provided in ASM
+;
+extern ASM_PFX(FspApiCommonContinue)
+extern ASM_PFX(AsmGetFspInfoHeader)
+
+;----------------------------------------------------------------------------
+; FspApiCommon API
+;
+; This is the FSP API common entry point to resume the FSP execution
+;
+;----------------------------------------------------------------------------
+global ASM_PFX(FspApiCommon)
+ASM_PFX(FspApiCommon):
+ ;
+ ; RAX holds the API index
+ ;
+
+ ;
+ ; Stack must be ready
+ ;
+ push rax
+ add rsp, 8
+ cmp rax, [rsp - 8]
+ jz FspApiCommon1
+ mov rax, 08000000000000003h
+ jmp exit
+
+FspApiCommon1:
+ ;
+ ; Verify the calling condition
+ ;
+ PUSHA_64
+ mov rdx, rcx ; move ApiParam to rdx
+ mov rcx, rax ; move ApiIdx to rcx
+ call ASM_PFX(FspApiCallingCheck)
+ cmp rax, 0
+ jz FspApiCommon2
+ mov [rsp + STACK_SAVED_RAX_OFFSET], rax
+ POPA_64
+exit:
+ ret
+
+FspApiCommon2:
+ POPA_64
+ cmp rax, 3 ; FspMemoryInit API
+ jz FspApiCommon3
+
+ cmp rax, 6 ; FspMultiPhaseSiInitApiIndex API
+ jz FspApiCommon3
+
+ call ASM_PFX(AsmGetFspInfoHeader)
+ jmp ASM_PFX(Loader2PeiSwitchStack)
+
+FspApiCommon3:
+ jmp ASM_PFX(FspApiCommonContinue)
+
|