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| author | Chasel Chiu <chasel.chiu@intel.com> | 2020-04-30 09:28:35 +0800 |
|---|---|---|
| committer | mergify[bot] <37929162+mergify[bot]@users.noreply.github.com> | 2020-05-14 12:34:01 +0000 |
| commit | f2cdb268ef04eeec51948b5d81eeca5cab5ed9af (patch) | |
| tree | 989349555cc3b783737d9aa2a6a56a67f7e63eac /IntelFsp2Pkg/FspSecCore/Fsp22SecCoreS.inf | |
| parent | ceacd9e992cd12f3c07ae1a28a75a6b8750718aa (diff) | |
| download | edk2-f2cdb268ef04eeec51948b5d81eeca5cab5ed9af.zip edk2-f2cdb268ef04eeec51948b5d81eeca5cab5ed9af.tar.gz edk2-f2cdb268ef04eeec51948b5d81eeca5cab5ed9af.tar.bz2 | |
IntelFsp2Pkg: Support Multi-Phase SiInit and debug handlers.
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=2698
To enhance FSP silicon initialization flexibility an optional
Multi-Phase API is introduced and FSP header needs update for
new API offset. Also new SecCore module created for
FspMultiPhaseSiInit API
New ARCH_UPD introduced for enhancing FSP debug message
flexibility now bootloader can pass its own debug handler
function pointer and FSP will call the function to handle
debug message.
To support calling bootloader functions, a FspGlobalData field
added to indicate if FSP needs to switch stack when FSP running
on separate stack from bootloader.
Cc: Maurice Ma <maurice.ma@intel.com>
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Cc: Star Zeng <star.zeng@intel.com>
Signed-off-by: Chasel Chiu <chasel.chiu@intel.com>
Reviewed-by: Nate DeSimone <nathaniel.l.desimone@intel.com>
Diffstat (limited to 'IntelFsp2Pkg/FspSecCore/Fsp22SecCoreS.inf')
| -rw-r--r-- | IntelFsp2Pkg/FspSecCore/Fsp22SecCoreS.inf | 52 |
1 files changed, 52 insertions, 0 deletions
diff --git a/IntelFsp2Pkg/FspSecCore/Fsp22SecCoreS.inf b/IntelFsp2Pkg/FspSecCore/Fsp22SecCoreS.inf new file mode 100644 index 0000000..0a24eb2 --- /dev/null +++ b/IntelFsp2Pkg/FspSecCore/Fsp22SecCoreS.inf @@ -0,0 +1,52 @@ +## @file
+# Sec Core for FSP to support MultiPhase (SeparatePhase) SiInitialization.
+#
+# Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = Fsp22SecCoreS
+ FILE_GUID = DF0FCD70-264A-40BF-BBD4-06C76DB19CB1
+ MODULE_TYPE = SEC
+ VERSION_STRING = 1.0
+
+#
+# The following information is for reference only and not required by the build tools.
+#
+# VALID_ARCHITECTURES = IA32
+#
+
+[Sources]
+ SecFspApiChk.c
+ SecFsp.h
+
+[Sources.IA32]
+ Ia32/Stack.nasm
+ Ia32/Fsp22ApiEntryS.nasm
+ Ia32/FspApiEntryCommon.nasm
+ Ia32/FspHelper.nasm
+
+[Binaries.Ia32]
+ RAW|Vtf0/Bin/ResetVec.ia32.raw |GCC
+
+[Packages]
+ MdePkg/MdePkg.dec
+ IntelFsp2Pkg/IntelFsp2Pkg.dec
+
+[LibraryClasses]
+ BaseMemoryLib
+ DebugLib
+ BaseLib
+ PciCf8Lib
+ SerialPortLib
+ FspSwitchStackLib
+ FspCommonLib
+ FspSecPlatformLib
+
+[Ppis]
+ gEfiTemporaryRamSupportPpiGuid ## PRODUCES
+
|