diff options
| author | li-elvin <li-elvin@6f19259b-4bc3-4df7-8a09-765794883524> | 2012-12-12 07:47:33 +0000 |
|---|---|---|
| committer | li-elvin <li-elvin@6f19259b-4bc3-4df7-8a09-765794883524> | 2012-12-12 07:47:33 +0000 |
| commit | 3e5eb447019c1ffcd3d28f2221cacf087174b119 (patch) | |
| tree | 00eeb42c3f7c9b64c048358d998d541731d7200d /IntelFrameworkModulePkg/Csm | |
| parent | b3d421700172b1673cb52b17bef676377207ed5a (diff) | |
| download | edk2-3e5eb447019c1ffcd3d28f2221cacf087174b119.zip edk2-3e5eb447019c1ffcd3d28f2221cacf087174b119.tar.gz edk2-3e5eb447019c1ffcd3d28f2221cacf087174b119.tar.bz2 | |
Remove hard code value and create new PCDs for OpROM reserved range in CSM module.
Signed-off-by: Li Elvin <elvin.li@intel.com>
Reviewed-by: Yao Jiewen <jiewen.yao@intel.com>
git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@13991 6f19259b-4bc3-4df7-8a09-765794883524
Diffstat (limited to 'IntelFrameworkModulePkg/Csm')
| -rw-r--r-- | IntelFrameworkModulePkg/Csm/LegacyBiosDxe/LegacyBios.c | 17 | ||||
| -rw-r--r-- | IntelFrameworkModulePkg/Csm/LegacyBiosDxe/LegacyBiosDxe.inf | 2 |
2 files changed, 17 insertions, 2 deletions
diff --git a/IntelFrameworkModulePkg/Csm/LegacyBiosDxe/LegacyBios.c b/IntelFrameworkModulePkg/Csm/LegacyBiosDxe/LegacyBios.c index 0381098..99a76c9 100644 --- a/IntelFrameworkModulePkg/Csm/LegacyBiosDxe/LegacyBios.c +++ b/IntelFrameworkModulePkg/Csm/LegacyBiosDxe/LegacyBios.c @@ -682,6 +682,7 @@ LegacyBiosInstall ( LEGACY_BIOS_INSTANCE *Private;
EFI_TO_COMPATIBILITY16_INIT_TABLE *EfiToLegacy16InitTable;
EFI_PHYSICAL_ADDRESS MemoryAddress;
+ EFI_PHYSICAL_ADDRESS EbdaReservedBaseAddress;
VOID *MemoryPtr;
EFI_PHYSICAL_ADDRESS MemoryAddressUnder1MB;
UINTN Index;
@@ -880,9 +881,21 @@ LegacyBiosInstall ( //
// Allocate all 32k chunks from 0x60000 ~ 0x88000 for Legacy OPROMs that
// don't use PMM but look for zeroed memory. Note that various non-BBS
- // SCSIs expect different areas to be free
+ // OpROMs expect different areas to be free
//
- for (MemStart = 0x60000; MemStart < 0x88000; MemStart += 0x1000) {
+ EbdaReservedBaseAddress = MemoryAddress;
+ MemoryAddress = PcdGet32 (PcdOpromReservedMemoryBase);
+ MemorySize = PcdGet32 (PcdOpromReservedMemorySize);
+ //
+ // Check if base address and size for reserved memory are 4KB aligned.
+ //
+ ASSERT ((MemoryAddress & 0xFFF) == 0);
+ ASSERT ((MemorySize & 0xFFF) == 0);
+ //
+ // Check if the reserved memory is below EBDA reserved range.
+ //
+ ASSERT ((MemoryAddress < EbdaReservedBaseAddress) && ((MemoryAddress + MemorySize - 1) < EbdaReservedBaseAddress));
+ for (MemStart = MemoryAddress; MemStart < MemoryAddress + MemorySize; MemStart += 0x1000) {
Status = AllocateLegacyMemory (
AllocateAddress,
MemStart,
diff --git a/IntelFrameworkModulePkg/Csm/LegacyBiosDxe/LegacyBiosDxe.inf b/IntelFrameworkModulePkg/Csm/LegacyBiosDxe/LegacyBiosDxe.inf index ea8cb6b..a5ad0df 100644 --- a/IntelFrameworkModulePkg/Csm/LegacyBiosDxe/LegacyBiosDxe.inf +++ b/IntelFrameworkModulePkg/Csm/LegacyBiosDxe/LegacyBiosDxe.inf @@ -140,6 +140,8 @@ gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdEndOpromShadowAddress
gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdLowPmmMemorySize
gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdHighPmmMemorySize
+ gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdOpromReservedMemoryBase
+ gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdOpromReservedMemorySize
[Depex]
gEfiLegacyRegion2ProtocolGuid AND gEfiLegacyInterruptProtocolGuid AND gEfiLegacyBiosPlatformProtocolGuid AND gEfiLegacy8259ProtocolGuid AND gEfiGenericMemTestProtocolGuid AND gEfiCpuArchProtocolGuid AND gEfiTimerArchProtocolGuid AND gEfiVariableWriteArchProtocolGuid
|