diff options
| author | Sami Mujawar <sami.mujawar@arm.com> | 2023-09-22 15:35:13 +0100 |
|---|---|---|
| committer | mergify[bot] <37929162+mergify[bot]@users.noreply.github.com> | 2023-10-30 12:16:56 +0000 |
| commit | 3ee23713e1ce09faa6fa66ee6799e3e336deb58b (patch) | |
| tree | 9bc1a16ab75f32499d660b0a4a14bd770680fa65 /FmpDevicePkg/PrivateInclude | |
| parent | f81ee47513e55e4748eccb2f941a5bb0cbf45612 (diff) | |
| download | edk2-3ee23713e1ce09faa6fa66ee6799e3e336deb58b.zip edk2-3ee23713e1ce09faa6fa66ee6799e3e336deb58b.tar.gz edk2-3ee23713e1ce09faa6fa66ee6799e3e336deb58b.tar.bz2 | |
DynamicTablesPkg: Add ETE device to CPU node in AML
The Coresight Embedded Trace Extension (ETE) feature
can be detected by the platform firmware by examining
the debug feature register ID_AA64DFR0_EL1.TraceVer
field.
The platform configuration manager can then describe
the ETE by creating CM_ARM_ET_INFO object(s) and
referencing these in CM_ARM_GICC_INFO.EtToken.
The 'Table 3: Compatible IDs for architected
CoreSight components' in the 'ACPI for CoreSight
1.2 Platform Design Document' specifies the HID
value for Coresight ETE and CoreSight Embedded
Trace Macrocell (ETM) v4.x as ARMH C500.
Therefore, update the SsdtCpuTopologyGenerator
to add an ETE device to the CPU node in the AML
CPU hierarchy so that an OS can utilise this
information.
Note: Although ETE and ETM share the same HID,
ETE has a system register interfaces, unlike
ETM which requires memory mapped registers.
Since this patch aims to support ETE, the AML
description does not describe any memory mapped
registers. However, support for ETM can be
added in the future.
Signed-off-by: Sami Mujawar <sami.mujawar@arm.com>
Reviewed-by: Pierre Gondois <pierre.gondois@arm.com>
Diffstat (limited to 'FmpDevicePkg/PrivateInclude')
0 files changed, 0 insertions, 0 deletions