diff options
| author | Maurice Ma <maurice.ma@intel.com> | 2016-05-16 15:02:44 -0700 |
|---|---|---|
| committer | Maurice Ma <maurice.ma@intel.com> | 2016-05-23 13:53:41 -0700 |
| commit | 69787a9d3115a0e50849de7a77c996c889b1e661 (patch) | |
| tree | 29dfbecc6a67dd6a414ccf1b4b4bae7130a93ab9 /CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc | |
| parent | 60c809f3621039bb1ac6b4c1947baf5a848814b0 (diff) | |
| download | edk2-69787a9d3115a0e50849de7a77c996c889b1e661.zip edk2-69787a9d3115a0e50849de7a77c996c889b1e661.tar.gz edk2-69787a9d3115a0e50849de7a77c996c889b1e661.tar.bz2 | |
CorebootPayloadPkg: Use generic PciBus/PciHostBridge driver
Current CorebootPayloadPkg uses PciBusNoEnumerationDxe and
PciRootBridgenoEnumerationDxe copied from the DuetPkg. Now it will
switch to use the standard PciBusDxe and PciHostBridgeDxe from
MdeModulePkg. As a result, a coreboot specific PciHostBridgeLib
is added to collect pre-allocated PCI resources.
Cc: Prince Agyeman <prince.agyeman@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
Reviewed-by: Prince Agyeman <prince.agyeman@intel.com>
Diffstat (limited to 'CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc')
| -rw-r--r-- | CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc | 20 |
1 files changed, 16 insertions, 4 deletions
diff --git a/CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc b/CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc index dcc0151..3950c00 100644 --- a/CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc +++ b/CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc @@ -39,6 +39,11 @@ DEFINE MAX_LOGICAL_PROCESSORS = 64
#
+ # PCI options
+ #
+ DEFINE PCIE_BASE = 0xE0000000
+
+ #
# Serial port set up
#
DEFINE BAUD_RATE = 115200
@@ -115,8 +120,9 @@ PrintLib|MdePkg/Library/BasePrintLib/BasePrintLib.inf
CpuLib|MdePkg/Library/BaseCpuLib/BaseCpuLib.inf
IoLib|MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf
- PciLib|MdePkg/Library/BasePciLibCf8/BasePciLibCf8.inf
- PciCf8Lib|MdePkg/Library/BasePciCf8Lib/BasePciCf8Lib.inf
+ PciLib|MdePkg/Library/BasePciLibPciExpress/BasePciLibPciExpress.inf
+ PciExpressLib|MdePkg/Library/BasePciExpressLib/BasePciExpressLib.inf
+ PciSegmentLib|MdePkg/Library/BasePciSegmentLibPci/BasePciSegmentLibPci.inf
PeCoffLib|MdePkg/Library/BasePeCoffLib/BasePeCoffLib.inf
PeCoffGetEntryPointLib|MdePkg/Library/BasePeCoffGetEntryPointLib/BasePeCoffGetEntryPointLib.inf
CacheMaintenanceLib|MdePkg/Library/BaseCacheMaintenanceLib/BaseCacheMaintenanceLib.inf
@@ -251,6 +257,8 @@ gEfiMdeModulePkgTokenSpaceGuid.PcdVpdBaseAddress|0x0
gEfiMdeModulePkgTokenSpaceGuid.PcdBootManagerMenuFile|{ 0x21, 0xaa, 0x2c, 0x46, 0x14, 0x76, 0x03, 0x45, 0x83, 0x6e, 0x8a, 0xb6, 0xf4, 0x66, 0x23, 0x31 }
+ gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|$(PCIE_BASE)
+
!if $(SOURCE_DEBUG_ENABLE)
gEfiSourceLevelDebugPkgTokenSpaceGuid.PcdDebugLoadImageMethod|0x2
!endif
@@ -282,6 +290,7 @@ gEfiMdeModulePkgTokenSpaceGuid.PcdSerialFifoControl|$(SERIAL_FIFO_CONTROL)
gEfiMdeModulePkgTokenSpaceGuid.PcdSerialExtendedTxFifoSize|$(SERIAL_EXTENDED_TX_FIFO_SIZE)
+ gEfiMdeModulePkgTokenSpaceGuid.PcdPciDisableBusEnumeration|TRUE
gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate|$(UART_DEFAULT_BAUD_RATE)
gEfiMdePkgTokenSpaceGuid.PcdUartDefaultDataBits|$(UART_DEFAULT_DATA_BITS)
gEfiMdePkgTokenSpaceGuid.PcdUartDefaultParity|$(UART_DEFAULT_PARITY)
@@ -418,8 +427,11 @@ #
# PCI Support
#
- CorebootModulePkg/PciRootBridgeNoEnumerationDxe/PciRootBridgeNoEnumeration.inf
- CorebootModulePkg/PciBusNoEnumerationDxe/PciBusNoEnumeration.inf
+ MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf
+ MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf {
+ <LibraryClasses>
+ PciHostBridgeLib|CorebootPayloadPkg/Library/PciHostBridgeLib/PciHostBridgeLib.inf
+ }
#
# SCSI/ATA/IDE/DISK Support
|