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| author | Brijesh Singh <brijesh.singh@amd.com> | 2022-02-21 22:59:14 +0800 |
|---|---|---|
| committer | mergify[bot] <37929162+mergify[bot]@users.noreply.github.com> | 2022-02-28 02:46:08 +0000 |
| commit | f1d1c337e7c0575da7fd248b2dd9cffc755940df (patch) | |
| tree | 217381b48a3f3789cc6689215121cdfb068fe047 /BaseTools/Source/Python | |
| parent | 63c50d3ff2854a76432b752af4f2a76f33ff1974 (diff) | |
| download | edk2-f1d1c337e7c0575da7fd248b2dd9cffc755940df.zip edk2-f1d1c337e7c0575da7fd248b2dd9cffc755940df.tar.gz edk2-f1d1c337e7c0575da7fd248b2dd9cffc755940df.tar.bz2 | |
OvmfPkg/BaseMemEncryptLib: use the SEV_STATUS MSR value from workarea
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3582
Improve the MemEncryptSev{Es,Snp}IsEnabled() to use the SEV_STATUS MSR
value saved in the workarea. Since workarea is valid until the PEI phase,
so, for the Dxe phase use the PcdConfidentialComputingGuestAttr to
determine which SEV technology is enabled.
Cc: Min Xu <min.m.xu@intel.com>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Tom Lendacky <thomas.lendacky@amd.com>
Cc: Jordan Justen <jordan.l.justen@intel.com>
Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>
Cc: Erdem Aktas <erdemaktas@google.com>
Cc: Gerd Hoffmann <kraxel@redhat.com>
Acked-by: Gerd Hoffmann <kraxel@redhat.com>
Signed-off-by: Brijesh Singh <brijesh.singh@amd.com>
Acked-by: Jiewen Yao <jiewen.yao@intel.com>
Diffstat (limited to 'BaseTools/Source/Python')
0 files changed, 0 insertions, 0 deletions