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| author | Sunil V L <sunilvl@ventanamicro.com> | 2022-12-15 11:02:43 +0530 |
|---|---|---|
| committer | mergify[bot] <37929162+mergify[bot]@users.noreply.github.com> | 2023-02-16 05:53:28 +0000 |
| commit | cbac2c74e803af7c6af1607d503906e3b2c46a2a (patch) | |
| tree | 427945a55fcde7c14bab495e729d1046679edafa /BaseTools/Source/Python/Pkcs7Sign | |
| parent | d6017bca19c4c716c5c672e8de2f67658184b6f2 (diff) | |
| download | edk2-cbac2c74e803af7c6af1607d503906e3b2c46a2a.zip edk2-cbac2c74e803af7c6af1607d503906e3b2c46a2a.tar.gz edk2-cbac2c74e803af7c6af1607d503906e3b2c46a2a.tar.bz2 | |
UefiCpuPkg: Add BaseRiscV64CpuExceptionHandlerLib
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4076
Add Cpu Exception Handler library for RISC-V. This is copied
from edk2-platforms/Silicon/RISC-V/ProcessorPkg/Library/RiscVExceptionLib
Cc: Eric Dong <eric.dong@intel.com>
Cc: Ray Ni <ray.ni@intel.com>
Cc: Rahul Kumar <rahul1.kumar@intel.com>
Cc: Daniel Schaefer <git@danielschaefer.me>
Cc: Abner Chang <abner.chang@amd.com>
Cc: Gerd Hoffmann <kraxel@redhat.com>
Signed-off-by: Sunil V L <sunilvl@ventanamicro.com>
Acked-by: Abner Chang <abner.chang@amd.com>
Reviewed-by: Andrei Warkentin <andrei.warkentin@intel.com>
Acked-by: Ray Ni <ray.ni@Intel.com>
Diffstat (limited to 'BaseTools/Source/Python/Pkcs7Sign')
0 files changed, 0 insertions, 0 deletions