ArmPlatformPkg/LcdGraphicsOutputDxe: Added support for ARM HDLCD controller (2)

... Forgot the new files



git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@13053 6f19259b-4bc3-4df7-8a09-765794883524

3 files changed, 274 insertions, 0 deletions

diff --git a/ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/HdLcd.c b/ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/HdLcd.c
new file mode 100644
index 0000000..c9baa98
--- /dev/null
+++ b/ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/HdLcd.c
@@ -0,0 +1,125 @@
+/** @file  Lcd.c

+

+  Copyright (c) 2011-2012, ARM Ltd. All rights reserved.<BR>

+

+  This program and the accompanying materials

+  are licensed and made available under the terms and conditions of the BSD License

+  which accompanies this distribution.  The full text of the license may be found at

+  http://opensource.org/licenses/bsd-license.php

+

+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,

+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.

+

+**/

+

+#include <Library/DebugLib.h>

+#include <Library/IoLib.h>

+#include <Library/LcdPlatformLib.h>

+#include <Library/MemoryAllocationLib.h>

+#include <Library/PcdLib.h>

+

+#include <Drivers/HdLcd.h>

+

+#include "LcdGraphicsOutputDxe.h"

+

+/**********************************************************************

+ *

+ *  This file contains all the bits of the Lcd that are

+ *  platform independent.

+ *

+ **********************************************************************/

+

+EFI_STATUS

+LcdInitialize (

+  IN EFI_PHYSICAL_ADDRESS   VramBaseAddress

+  )

+{

+  // Disable the controller

+  MmioWrite32(HDLCD_REG_COMMAND, HDLCD_DISABLE);

+

+  // Disable all interrupts

+  MmioWrite32(HDLCD_REG_INT_MASK, 0);

+

+  // Define start of the VRAM. This never changes for any graphics mode

+  MmioWrite32(HDLCD_REG_FB_BASE, (UINT32) VramBaseAddress);

+

+  // Setup various registers that never change

+  MmioWrite32(HDLCD_REG_BUS_OPTIONS,  (4 << 8) | HDLCD_BURST_8);

+  MmioWrite32(HDLCD_REG_POLARITIES,   HDLCD_PXCLK_LOW | HDLCD_DATA_HIGH | HDLCD_DATEN_HIGH | HDLCD_HSYNC_LOW | HDLCD_VSYNC_HIGH);

+  MmioWrite32(HDLCD_REG_PIXEL_FORMAT, HDLCD_LITTLE_ENDIAN | HDLCD_4BYTES_PER_PIXEL);

+  MmioWrite32(HDLCD_REG_RED_SELECT,   (0 << 16 | 8 << 8 |  0));

+  MmioWrite32(HDLCD_REG_GREEN_SELECT, (0 << 16 | 8 << 8 |  8));

+  MmioWrite32(HDLCD_REG_BLUE_SELECT,  (0 << 16 | 8 << 8 | 16));

+

+  return EFI_SUCCESS;

+}

+

+EFI_STATUS

+LcdSetMode (

+  IN UINT32  ModeNumber

+  )

+{

+  EFI_STATUS        Status;

+  UINT32            HRes;

+  UINT32            HSync;

+  UINT32            HBackPorch;

+  UINT32            HFrontPorch;

+  UINT32            VRes;

+  UINT32            VSync;

+  UINT32            VBackPorch;

+  UINT32            VFrontPorch;

+  UINT32            BytesPerPixel;

+  LCD_BPP           LcdBpp;

+

+

+  // Set the video mode timings and other relevant information

+  Status = LcdPlatformGetTimings (ModeNumber,

+                                  &HRes,&HSync,&HBackPorch,&HFrontPorch,

+                                  &VRes,&VSync,&VBackPorch,&VFrontPorch);

+  ASSERT_EFI_ERROR (Status);

+  if (EFI_ERROR( Status )) {

+    return EFI_DEVICE_ERROR;

+  }

+

+  Status = LcdPlatformGetBpp (ModeNumber,&LcdBpp);

+  ASSERT_EFI_ERROR (Status);

+  if (EFI_ERROR( Status )) {

+    return EFI_DEVICE_ERROR;

+  }

+

+  BytesPerPixel = GetBytesPerPixel(LcdBpp);

+

+  // Disable the controller

+  MmioWrite32(HDLCD_REG_COMMAND, HDLCD_DISABLE);

+

+  // Update the frame buffer information with the new settings

+  MmioWrite32(HDLCD_REG_FB_LINE_LENGTH, HRes * BytesPerPixel);

+  MmioWrite32(HDLCD_REG_FB_LINE_PITCH,  HRes * BytesPerPixel);

+  MmioWrite32(HDLCD_REG_FB_LINE_COUNT,  VRes - 1);

+

+  // Set the vertical timing information

+  MmioWrite32(HDLCD_REG_V_SYNC,         VSync);

+  MmioWrite32(HDLCD_REG_V_BACK_PORCH,   VBackPorch);

+  MmioWrite32(HDLCD_REG_V_DATA,         VRes - 1);

+  MmioWrite32(HDLCD_REG_V_FRONT_PORCH,  VFrontPorch);

+

+  // Set the horizontal timing information

+  MmioWrite32(HDLCD_REG_H_SYNC,         HSync);

+  MmioWrite32(HDLCD_REG_H_BACK_PORCH,   HBackPorch);

+  MmioWrite32(HDLCD_REG_H_DATA,         HRes - 1);

+  MmioWrite32(HDLCD_REG_H_FRONT_PORCH,  HFrontPorch);

+

+  // Enable the controller

+  MmioWrite32(HDLCD_REG_COMMAND, HDLCD_ENABLE);

+

+  return EFI_SUCCESS;

+}

+

+VOID

+LcdShutdown (

+  VOID

+  )

+{

+  // Nothing to do in terms of hardware.

+  // We could switch off the monitor display if required

+}

diff --git a/ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/HdLcdGraphicsOutputDxe.inf b/ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/HdLcdGraphicsOutputDxe.inf
new file mode 100644
index 0000000..ac61bf7
--- /dev/null
+++ b/ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/HdLcdGraphicsOutputDxe.inf
@@ -0,0 +1,60 @@
+#/** @file

+#  

+#  Component description file for HDLCD module

+#  

+#  Copyright (c) 2011-2012, ARM Ltd. All rights reserved.<BR>

+#  

+#  This program and the accompanying materials

+#  are licensed and made available under the terms and conditions of the BSD License

+#  which accompanies this distribution.  The full text of the license may be found at

+#  http://opensource.org/licenses/bsd-license.php

+#  

+#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,

+#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.

+#  

+#**/

+

+[Defines]

+  INF_VERSION                    = 0x00010005

+  BASE_NAME                      = HdLcdGraphicsDxe

+  FILE_GUID                      = ce660500-824d-11e0-ac72-0002a5d5c51b

+  MODULE_TYPE                    = DXE_DRIVER

+  VERSION_STRING                 = 1.0

+  ENTRY_POINT                    = LcdGraphicsOutputDxeInitialize

+

+[Sources.common]

+  LcdGraphicsOutputDxe.c

+  LcdGraphicsOutputBlt.c

+  HdLcd.c

+

+[Packages]

+  MdePkg/MdePkg.dec

+  MdeModulePkg/MdeModulePkg.dec

+  ArmPkg/ArmPkg.dec

+  ArmPlatformPkg/ArmVExpressPkg/ArmVExpressPkg.dec

+  ArmPlatformPkg/ArmPlatformPkg.dec

+

+[LibraryClasses]

+  ArmLib

+  UefiLib

+  BaseLib

+  DebugLib

+  TimerLib

+  UefiDriverEntryPoint

+  UefiBootServicesTableLib

+  IoLib

+  BaseMemoryLib

+  LcdPlatformLib

+

+[Protocols]

+  gEfiDevicePathProtocolGuid

+  gEfiGraphicsOutputProtocolGuid                # Produced

+  gEfiEdidDiscoveredProtocolGuid                # Produced

+  gEfiEdidActiveProtocolGuid                    # Produced

+  gEfiEdidOverrideProtocolGuid                  # Produced  

+

+[FixedPcd]

+  gArmPlatformTokenSpaceGuid.PcdArmHdLcdBase

+

+[Depex]

+  gEfiCpuArchProtocolGuid

diff --git a/ArmPlatformPkg/Include/Drivers/HdLcd.h b/ArmPlatformPkg/Include/Drivers/HdLcd.h
new file mode 100644
index 0000000..6df97a9
--- /dev/null
+++ b/ArmPlatformPkg/Include/Drivers/HdLcd.h
@@ -0,0 +1,89 @@
+/** @file  HDLcd.h

+

+ Copyright (c) 2011-2012, ARM Ltd. All rights reserved.<BR>

+

+ This program and the accompanying materials

+ are licensed and made available under the terms and conditions of the BSD License

+ which accompanies this distribution.  The full text of the license may be found at

+ http://opensource.org/licenses/bsd-license.php

+

+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,

+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.

+

+ **/

+

+#ifndef _HDLCD_H_

+#define _HDLCD_H_

+

+//

+// HDLCD Controller Register Offsets

+//

+

+#define HDLCD_REG_VERSION                 ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x000)

+#define HDLCD_REG_INT_RAWSTAT             ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x010)

+#define HDLCD_REG_INT_CLEAR               ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x014)

+#define HDLCD_REG_INT_MASK                ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x018)

+#define HDLCD_REG_INT_STATUS              ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x01C)

+#define HDLCD_REG_FB_BASE                 ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x100)

+#define HDLCD_REG_FB_LINE_LENGTH          ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x104)

+#define HDLCD_REG_FB_LINE_COUNT           ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x108)

+#define HDLCD_REG_FB_LINE_PITCH           ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x10C)

+#define HDLCD_REG_BUS_OPTIONS             ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x110)

+#define HDLCD_REG_V_SYNC                  ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x200)

+#define HDLCD_REG_V_BACK_PORCH            ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x204)

+#define HDLCD_REG_V_DATA                  ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x208)

+#define HDLCD_REG_V_FRONT_PORCH           ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x20C)

+#define HDLCD_REG_H_SYNC                  ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x210)

+#define HDLCD_REG_H_BACK_PORCH            ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x214)

+#define HDLCD_REG_H_DATA                  ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x218)

+#define HDLCD_REG_H_FRONT_PORCH           ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x21C)

+#define HDLCD_REG_POLARITIES              ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x220)

+#define HDLCD_REG_COMMAND                 ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x230)

+#define HDLCD_REG_PIXEL_FORMAT            ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x240)

+#define HDLCD_REG_RED_SELECT              ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x244)

+#define HDLCD_REG_GREEN_SELECT            ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x248)

+#define HDLCD_REG_BLUE_SELECT             ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x24C)

+

+

+//

+// HDLCD Values of registers

+//

+

+// HDLCD Interrupt mask, clear and status register

+#define HDLCD_DMA_END                     BIT0    /* DMA has finished reading a frame */

+#define HDLCD_BUS_ERROR                   BIT1    /* DMA bus error */

+#define HDLCD_SYNC                        BIT2    /* Vertical sync */

+#define HDLCD_UNDERRUN                    BIT3    /* No Data available while DATAEN active */

+

+// CLCD_CONTROL Control register

+#define HDLCD_DISABLE                     0

+#define HDLCD_ENABLE                      BIT0

+

+// Bus Options

+#define HDLCD_BURST_1                     BIT0

+#define HDLCD_BURST_2                     BIT1

+#define HDLCD_BURST_4                     BIT2

+#define HDLCD_BURST_8                     BIT3

+#define HDLCD_BURST_16                    BIT4

+

+// Polarities - HIGH

+#define HDLCD_VSYNC_HIGH                  BIT0

+#define HDLCD_HSYNC_HIGH                  BIT1

+#define HDLCD_DATEN_HIGH                  BIT2

+#define HDLCD_DATA_HIGH                   BIT3

+#define HDLCD_PXCLK_HIGH                  BIT4

+// Polarities - LOW (for completion and for ease of understanding the hardware settings)

+#define HDLCD_VSYNC_LOW                   0

+#define HDLCD_HSYNC_LOW                   0

+#define HDLCD_DATEN_LOW                   0

+#define HDLCD_DATA_LOW                    0

+#define HDLCD_PXCLK_LOW                   0

+

+// Pixel Format

+#define HDLCD_LITTLE_ENDIAN              (0 << 31)

+#define HDLCD_BIG_ENDIAN                 (1 << 31)

+

+// Number of bytes per pixel

+#define HDLCD_4BYTES_PER_PIXEL           ((4 - 1) << 3)

+

+#endif /* _HDLCD_H_ */