ArmPlatformPkg: Timer access for non-secure EL1/0

According to Section 2.3.6 of the "UEFI Specification 2.6 Errata A";
the primary CPU must be configured such that 'Timer access must be
provided to non-secure EL1 and EL0 by setting bits EL1PCTEN and
EL1PCEN in register CNTHCTL_EL2.'

This commit adds this missing set-up to the PrePi and PrePeiCore
modules.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Sami Mujawar <sami.mujawar@arm.com>
Signed-off-by: Evan Lloyd <evan.lloyd@arm.com>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>

1 files changed, 8 insertions, 1 deletions

diff --git a/ArmPlatformPkg/PrePi/AArch64/ArchPrePi.c b/ArmPlatformPkg/PrePi/AArch64/ArchPrePi.c
index 2179861..4da5908 100644
--- a/ArmPlatformPkg/PrePi/AArch64/ArchPrePi.c
+++ b/ArmPlatformPkg/PrePi/AArch64/ArchPrePi.c
@@ -1,6 +1,6 @@
 /** @file

 *

-*  Copyright (c) 2011-2013, ARM Limited. All rights reserved.

+*  Copyright (c) 2011-2017, ARM Limited. All rights reserved.

 *

 *  This program and the accompanying materials

 *  are licensed and made available under the terms and conditions of the BSD License

@@ -29,5 +29,12 @@ ArchInitialize (
   if (ArmReadCurrentEL () == AARCH64_EL2) {

     // Trap General Exceptions. All exceptions that would be routed to EL1 are routed to EL2

     ArmWriteHcr (ARM_HCR_TGE);

+

+    /* Enable Timer access for non-secure EL1 and EL0

+       The cnthctl_el2 register bits are architecturally

+       UNKNOWN on reset.

+       Disable event stream as it is not in use at this stage

+    */

+    ArmWriteCntHctl (CNTHCTL_EL2_EL1PCTEN | CNTHCTL_EL2_EL1PCEN);

   }

 }