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| author | Ard Biesheuvel <ard.biesheuvel@linaro.org> | 2016-09-09 09:01:56 +0100 |
|---|---|---|
| committer | Ard Biesheuvel <ard.biesheuvel@linaro.org> | 2016-09-13 13:43:34 +0100 |
| commit | dd82465a9f0f0beff0e4d74c6e3192b966853332 (patch) | |
| tree | 5bb8c1aa39b134a058b568c53a7ebe59e30ad297 /ArmPkg | |
| parent | d32702d2c2aa23e828363a7f88829b78ce36c3af (diff) | |
| download | edk2-dd82465a9f0f0beff0e4d74c6e3192b966853332.zip edk2-dd82465a9f0f0beff0e4d74c6e3192b966853332.tar.gz edk2-dd82465a9f0f0beff0e4d74c6e3192b966853332.tar.bz2 | |
ArmPkg/ArmMmuLib: base page table VA size on GCD memory map size
As reported by Eugene, the practice of sizing the address space in the
virtual memory system based on the maximum address in the table passed
to ArmConfigureMmu() is problematic, since it fails to take into account
the fact that the GCD memory space may be extended at a later time, both
for memory and for MMIO. So instead, choose the VA size identical to the
GCD memory map size, which is based on PcdPrePiCpuMemorySize on ARM
systems.
Reported-by: Eugene Cohen <eugene@hp.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Eugene Cohen <eugene@hp.com>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
Diffstat (limited to 'ArmPkg')
| -rw-r--r-- | ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibCore.c | 14 | ||||
| -rw-r--r-- | ArmPkg/Library/ArmMmuLib/ArmMmuBaseLib.inf | 4 | ||||
| -rw-r--r-- | ArmPkg/Library/ArmMmuLib/ArmMmuPeiLib.inf | 4 |
3 files changed, 10 insertions, 12 deletions
diff --git a/ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibCore.c b/ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibCore.c index 57e789f..1fb3bbe 100644 --- a/ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibCore.c +++ b/ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibCore.c @@ -555,9 +555,7 @@ ArmConfigureMmu ( VOID* TranslationTable;
VOID* TranslationTableBuffer;
UINT32 TranslationTableAttribute;
- ARM_MEMORY_REGION_DESCRIPTOR *MemoryTableEntry;
UINT64 MaxAddress;
- UINT64 TopAddress;
UINTN T0SZ;
UINTN RootTableEntryCount;
UINTN RootTableEntrySize;
@@ -569,16 +567,8 @@ ArmConfigureMmu ( return RETURN_INVALID_PARAMETER;
}
- // Identify the highest address of the memory table
- MaxAddress = MemoryTable->PhysicalBase + MemoryTable->Length - 1;
- MemoryTableEntry = MemoryTable;
- while (MemoryTableEntry->Length != 0) {
- TopAddress = MemoryTableEntry->PhysicalBase + MemoryTableEntry->Length - 1;
- if (TopAddress > MaxAddress) {
- MaxAddress = TopAddress;
- }
- MemoryTableEntry++;
- }
+ // Cover the entire GCD memory space
+ MaxAddress = (1UL << PcdGet8 (PcdPrePiCpuMemorySize)) - 1;
// Lookup the Table Level to get the information
LookupAddresstoRootTable (MaxAddress, &T0SZ, &RootTableEntryCount);
diff --git a/ArmPkg/Library/ArmMmuLib/ArmMmuBaseLib.inf b/ArmPkg/Library/ArmMmuLib/ArmMmuBaseLib.inf index 1533c29..b9f264d 100644 --- a/ArmPkg/Library/ArmMmuLib/ArmMmuBaseLib.inf +++ b/ArmPkg/Library/ArmMmuLib/ArmMmuBaseLib.inf @@ -32,6 +32,7 @@ [Packages]
ArmPkg/ArmPkg.dec
+ EmbeddedPkg/EmbeddedPkg.dec
MdePkg/MdePkg.dec
[LibraryClasses]
@@ -39,5 +40,8 @@ CacheMaintenanceLib
MemoryAllocationLib
+[Pcd.AARCH64]
+ gEmbeddedTokenSpaceGuid.PcdPrePiCpuMemorySize
+
[Pcd.ARM]
gArmTokenSpaceGuid.PcdNormalMemoryNonshareableOverride
diff --git a/ArmPkg/Library/ArmMmuLib/ArmMmuPeiLib.inf b/ArmPkg/Library/ArmMmuLib/ArmMmuPeiLib.inf index 14ebf8d..ecf13f7 100644 --- a/ArmPkg/Library/ArmMmuLib/ArmMmuPeiLib.inf +++ b/ArmPkg/Library/ArmMmuLib/ArmMmuPeiLib.inf @@ -28,9 +28,13 @@ [Packages]
ArmPkg/ArmPkg.dec
+ EmbeddedPkg/EmbeddedPkg.dec
MdePkg/MdePkg.dec
[LibraryClasses]
ArmLib
CacheMaintenanceLib
MemoryAllocationLib
+
+[Pcd.AARCH64]
+ gEmbeddedTokenSpaceGuid.PcdPrePiCpuMemorySize
|