ArmPkg,MdePkg: Move ArmPkg/Chipset/ArmV7[|Mmu].h to MdePkg

Following the discussion at [1] and as the ArmLib relies on them,
move ArmPkg/Chipset/ArmV7[|Mmu].h files to the MdePkg.

Update the path to correctly include the moved files.

[1] https://edk2.groups.io/g/devel/message/111566

Continuous-integration-options: PatchCheck.ignore-multi-package
Signed-off-by: Pierre Gondois <pierre.gondois@arm.com>
Acked-by: Ard Biesheuvel <ardb@kernel.org>
Reviewed-by: Leif Lindholm <quic_llindhol@quicinc.com>

7 files changed, 5 insertions, 452 deletions

diff --git a/ArmPkg/Include/Chipset/AArch64.h b/ArmPkg/Include/Chipset/AArch64.h
deleted file mode 100644
index 5390bf0..0000000
--- a/ArmPkg/Include/Chipset/AArch64.h
+++ /dev/null
@@ -1,252 +0,0 @@
-/** @file

-

-  Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>

-  Copyright (c) 2011 - 2021, Arm Limited. All rights reserved.<BR>

-

-  SPDX-License-Identifier: BSD-2-Clause-Patent

-

-**/

-

-#ifndef AARCH64_H_

-#define AARCH64_H_

-

-#include <Chipset/AArch64Mmu.h>

-

-// ARM Interrupt ID in Exception Table

-#define ARM_ARCH_EXCEPTION_IRQ  EXCEPT_AARCH64_IRQ

-

-// CPACR - Coprocessor Access Control Register definitions

-#define CPACR_TTA_EN          (1UL << 28)

-#define CPACR_FPEN_EL1        (1UL << 20)

-#define CPACR_FPEN_FULL       (3UL << 20)

-#define CPACR_CP_FULL_ACCESS  0x300000

-

-// Coprocessor Trap Register (CPTR)

-#define AARCH64_CPTR_TFP  (1 << 10)

-

-// ID_AA64MMFR1 - AArch64 Memory Model Feature Register 0 definitions

-#define AARCH64_MMFR1_VH  (0xF << 8)

-

-// ID_AA64PFR0 - AArch64 Processor Feature Register 0 definitions

-#define AARCH64_PFR0_FP   (0xF << 16)

-#define AARCH64_PFR0_GIC  (0xF << 24)

-

-// ID_AA64DFR0 - AArch64 Debug Feature Register 0 definitions

-#define AARCH64_DFR0_TRACEVER  (0xFULL << 4)

-#define AARCH64_DFR0_TRBE      (0xFULL << 44)

-

-// SCR - Secure Configuration Register definitions

-#define SCR_NS   (1 << 0)

-#define SCR_IRQ  (1 << 1)

-#define SCR_FIQ  (1 << 2)

-#define SCR_EA   (1 << 3)

-#define SCR_FW   (1 << 4)

-#define SCR_AW   (1 << 5)

-

-// MIDR - Main ID Register definitions

-#define ARM_CPU_TYPE_SHIFT  4

-#define ARM_CPU_TYPE_MASK   0xFFF

-#define ARM_CPU_TYPE_AEMV8  0xD0F

-#define ARM_CPU_TYPE_A53    0xD03

-#define ARM_CPU_TYPE_A57    0xD07

-#define ARM_CPU_TYPE_A72    0xD08

-#define ARM_CPU_TYPE_A15    0xC0F

-#define ARM_CPU_TYPE_A9     0xC09

-#define ARM_CPU_TYPE_A7     0xC07

-#define ARM_CPU_TYPE_A5     0xC05

-

-#define ARM_CPU_REV_MASK  ((0xF << 20) | (0xF) )

-#define ARM_CPU_REV(rn, pn)  ((((rn) & 0xF) << 20) | ((pn) & 0xF))

-

-// Hypervisor Configuration Register

-#define ARM_HCR_FMO  BIT3

-#define ARM_HCR_IMO  BIT4

-#define ARM_HCR_AMO  BIT5

-#define ARM_HCR_TSC  BIT19

-#define ARM_HCR_TGE  BIT27

-

-// Exception Syndrome Register

-#define AARCH64_ESR_EC(Ecr)   ((0x3F << 26) & (Ecr))

-#define AARCH64_ESR_ISS(Ecr)  ((0x1FFFFFF) & (Ecr))

-

-#define AARCH64_ESR_EC_SMC32  (0x13 << 26)

-#define AARCH64_ESR_EC_SMC64  (0x17 << 26)

-

-// AArch64 Exception Level

-#define AARCH64_EL3  0xC

-#define AARCH64_EL2  0x8

-#define AARCH64_EL1  0x4

-

-// Saved Program Status Register definitions

-#define SPSR_A  BIT8

-#define SPSR_I  BIT7

-#define SPSR_F  BIT6

-

-#define SPSR_AARCH32  BIT4

-

-#define SPSR_AARCH32_MODE_USER   0x0

-#define SPSR_AARCH32_MODE_FIQ    0x1

-#define SPSR_AARCH32_MODE_IRQ    0x2

-#define SPSR_AARCH32_MODE_SVC    0x3

-#define SPSR_AARCH32_MODE_ABORT  0x7

-#define SPSR_AARCH32_MODE_UNDEF  0xB

-#define SPSR_AARCH32_MODE_SYS    0xF

-

-// Counter-timer Hypervisor Control register definitions

-#define CNTHCTL_EL2_EL1PCTEN  BIT0

-#define CNTHCTL_EL2_EL1PCEN   BIT1

-

-#define ARM_VECTOR_TABLE_ALIGNMENT  ((1 << 11)-1)

-

-// Vector table offset definitions

-#define ARM_VECTOR_CUR_SP0_SYNC  0x000

-#define ARM_VECTOR_CUR_SP0_IRQ   0x080

-#define ARM_VECTOR_CUR_SP0_FIQ   0x100

-#define ARM_VECTOR_CUR_SP0_SERR  0x180

-

-#define ARM_VECTOR_CUR_SPX_SYNC  0x200

-#define ARM_VECTOR_CUR_SPX_IRQ   0x280

-#define ARM_VECTOR_CUR_SPX_FIQ   0x300

-#define ARM_VECTOR_CUR_SPX_SERR  0x380

-

-#define ARM_VECTOR_LOW_A64_SYNC  0x400

-#define ARM_VECTOR_LOW_A64_IRQ   0x480

-#define ARM_VECTOR_LOW_A64_FIQ   0x500

-#define ARM_VECTOR_LOW_A64_SERR  0x580

-

-#define ARM_VECTOR_LOW_A32_SYNC  0x600

-#define ARM_VECTOR_LOW_A32_IRQ   0x680

-#define ARM_VECTOR_LOW_A32_FIQ   0x700

-#define ARM_VECTOR_LOW_A32_SERR  0x780

-

-// The ID_AA64ISAR2_EL1 register is not recognized by older

-// assemblers, we need to define it here.

-#define ID_AA64ISAR2_EL1  S3_0_C0_C6_2

-

-// The ID_AA64MMFR2_EL1 register was added in ARMv8.2. Since we

-// build for ARMv8.0, we need to define the register here.

-#define ID_AA64MMFR2_EL1  S3_0_C0_C7_2

-

-#define VECTOR_BASE(tbl)          \

-  .section .text.##tbl##,"ax";    \

-  .align 11;                      \

-  .org 0x0;                       \

-  GCC_ASM_EXPORT(tbl);            \

-  ASM_PFX(tbl):                   \

-

-#define VECTOR_ENTRY(tbl, off)    \

-  .org off

-

-#define VECTOR_END(tbl)           \

-  .org 0x800;                     \

-  .previous

-

-VOID

-EFIAPI

-ArmEnableSWPInstruction (

-  VOID

-  );

-

-UINTN

-EFIAPI

-ArmReadCbar (

-  VOID

-  );

-

-UINTN

-EFIAPI

-ArmReadTpidrurw (

-  VOID

-  );

-

-VOID

-EFIAPI

-ArmWriteTpidrurw (

-  UINTN  Value

-  );

-

-UINTN

-EFIAPI

-ArmGetTCR (

-  VOID

-  );

-

-VOID

-EFIAPI

-ArmSetTCR (

-  UINTN  Value

-  );

-

-UINTN

-EFIAPI

-ArmGetMAIR (

-  VOID

-  );

-

-VOID

-EFIAPI

-ArmSetMAIR (

-  UINTN  Value

-  );

-

-VOID

-EFIAPI

-ArmDisableAlignmentCheck (

-  VOID

-  );

-

-VOID

-EFIAPI

-ArmEnableAlignmentCheck (

-  VOID

-  );

-

-VOID

-EFIAPI

-ArmDisableStackAlignmentCheck (

-  VOID

-  );

-

-VOID

-EFIAPI

-ArmEnableStackAlignmentCheck (

-  VOID

-  );

-

-VOID

-EFIAPI

-ArmDisableAllExceptions (

-  VOID

-  );

-

-VOID

-ArmWriteHcr (

-  IN UINTN  Hcr

-  );

-

-UINTN

-ArmReadHcr (

-  VOID

-  );

-

-UINTN

-ArmReadCurrentEL (

-  VOID

-  );

-

-UINTN

-ArmWriteCptr (

-  IN  UINT64  Cptr

-  );

-

-UINT32

-ArmReadCntHctl (

-  VOID

-  );

-

-VOID

-ArmWriteCntHctl (

-  IN UINT32  CntHctl

-  );

-

-#endif // AARCH64_H_

diff --git a/ArmPkg/Include/Chipset/AArch64Mmu.h b/ArmPkg/Include/Chipset/AArch64Mmu.h
deleted file mode 100644
index 2ea2cc0..0000000
--- a/ArmPkg/Include/Chipset/AArch64Mmu.h
+++ /dev/null
@@ -1,195 +0,0 @@
-/** @file

-*

-*  Copyright (c) 2011-2021, Arm Limited. All rights reserved.<BR>

-*

-*  SPDX-License-Identifier: BSD-2-Clause-Patent

-*

-**/

-

-#ifndef AARCH64_MMU_H_

-#define AARCH64_MMU_H_

-

-//

-// Memory Attribute Indirection register Definitions

-//

-#define MAIR_ATTR_DEVICE_MEMORY                0x0ULL

-#define MAIR_ATTR_NORMAL_MEMORY_NON_CACHEABLE  0x44ULL

-#define MAIR_ATTR_NORMAL_MEMORY_WRITE_THROUGH  0xBBULL

-#define MAIR_ATTR_NORMAL_MEMORY_WRITE_BACK     0xFFULL

-

-#define MAIR_ATTR(n, value)  ((value) << (((n) >> 2)*8))

-

-//

-// Long-descriptor Translation Table format

-//

-

-// Return the smallest offset from the table level.

-// The first offset starts at 12bit. There are 4 levels of 9-bit address range from level 3 to level 0

-#define TT_ADDRESS_OFFSET_AT_LEVEL(TableLevel)  (12 + ((3 - (TableLevel)) * 9))

-

-#define TT_BLOCK_ENTRY_SIZE_AT_LEVEL(Level)  (1ULL << TT_ADDRESS_OFFSET_AT_LEVEL(Level))

-

-// Get the associated entry in the given Translation Table

-#define TT_GET_ENTRY_FOR_ADDRESS(TranslationTable, Level, Address)  \

-    ((UINTN)(TranslationTable) + ((((UINTN)(Address) >> TT_ADDRESS_OFFSET_AT_LEVEL(Level)) & (BIT9-1)) * sizeof(UINT64)))

-

-// Return the smallest address granularity from the table level.

-// The first offset starts at 12bit. There are 4 levels of 9-bit address range from level 3 to level 0

-#define TT_ADDRESS_AT_LEVEL(TableLevel)  (1ULL << TT_ADDRESS_OFFSET_AT_LEVEL(TableLevel))

-

-#define TT_LAST_BLOCK_ADDRESS(TranslationTable, EntryCount) \

-    ((UINT64*)((EFI_PHYSICAL_ADDRESS)(TranslationTable) + (((EntryCount) - 1) * sizeof(UINT64))))

-

-// There are 512 entries per table when 4K Granularity

-#define TT_ENTRY_COUNT                  512

-#define TT_ALIGNMENT_BLOCK_ENTRY        BIT12

-#define TT_ALIGNMENT_DESCRIPTION_TABLE  BIT12

-

-#define TT_ADDRESS_MASK_BLOCK_ENTRY        (0xFFFFFFFFFULL << 12)

-#define TT_ADDRESS_MASK_DESCRIPTION_TABLE  (0xFFFFFFFFFULL << 12)

-

-#define TT_TYPE_MASK                0x3

-#define TT_TYPE_TABLE_ENTRY         0x3

-#define TT_TYPE_BLOCK_ENTRY         0x1

-#define TT_TYPE_BLOCK_ENTRY_LEVEL3  0x3

-

-#define TT_ATTR_INDX_MASK                  (0x7 << 2)

-#define TT_ATTR_INDX_DEVICE_MEMORY         (0x0 << 2)

-#define TT_ATTR_INDX_MEMORY_NON_CACHEABLE  (0x1 << 2)

-#define TT_ATTR_INDX_MEMORY_WRITE_THROUGH  (0x2 << 2)

-#define TT_ATTR_INDX_MEMORY_WRITE_BACK     (0x3 << 2)

-

-#define TT_AP_MASK   (0x3UL << 6)

-#define TT_AP_NO_RW  (0x0UL << 6)

-#define TT_AP_RW_RW  (0x1UL << 6)

-#define TT_AP_NO_RO  (0x2UL << 6)

-#define TT_AP_RO_RO  (0x3UL << 6)

-

-#define TT_NS  BIT5

-#define TT_AF  BIT10

-

-#define TT_SH_NON_SHAREABLE    (0x0 << 8)

-#define TT_SH_OUTER_SHAREABLE  (0x2 << 8)

-#define TT_SH_INNER_SHAREABLE  (0x3 << 8)

-#define TT_SH_MASK             (0x3 << 8)

-

-#define TT_PXN_MASK  BIT53

-#define TT_UXN_MASK  BIT54                              // EL1&0

-#define TT_XN_MASK   BIT54                              // EL2 / EL3

-

-#define TT_ATTRIBUTES_MASK  ((0xFFFULL << 52) | (0x3FFULL << 2))

-

-#define TT_TABLE_PXN  BIT59

-#define TT_TABLE_UXN  BIT60                             // EL1&0

-#define TT_TABLE_XN   BIT60                             // EL2 / EL3

-#define TT_TABLE_NS   BIT63

-

-#define TT_TABLE_AP_MASK             (BIT62 | BIT61)

-#define TT_TABLE_AP_NO_PERMISSION    (0x0ULL << 61)

-#define TT_TABLE_AP_EL0_NO_ACCESS    (0x1ULL << 61)

-#define TT_TABLE_AP_NO_WRITE_ACCESS  (0x2ULL << 61)

-

-//

-// Translation Control Register

-//

-#define TCR_T0SZ_MASK  0x3FUL

-

-#define TCR_PS_4GB    (0UL << 16)

-#define TCR_PS_64GB   (1UL << 16)

-#define TCR_PS_1TB    (2UL << 16)

-#define TCR_PS_4TB    (3UL << 16)

-#define TCR_PS_16TB   (4UL << 16)

-#define TCR_PS_256TB  (5UL << 16)

-

-#define TCR_TG0_4KB  (0UL << 14)

-#define TCR_TG1_4KB  (2UL << 30)

-

-#define TCR_IPS_4GB    (0ULL << 32)

-#define TCR_IPS_64GB   (1ULL << 32)

-#define TCR_IPS_1TB    (2ULL << 32)

-#define TCR_IPS_4TB    (3ULL << 32)

-#define TCR_IPS_16TB   (4ULL << 32)

-#define TCR_IPS_256TB  (5ULL << 32)

-

-#define TCR_EPD1  (1UL << 23)

-

-#define TTBR_ASID_FIELD  (48)

-#define TTBR_ASID_MASK   (0xFF << TTBR_ASID_FIELD)

-#define TTBR_BADDR_MASK  (0xFFFFFFFFFFFF )                     // The width of this field depends on the values in TxSZ. Addr occupies bottom 48bits

-

-#define TCR_EL1_T0SZ_FIELD   (0)

-#define TCR_EL1_EPD0_FIELD   (7)

-#define TCR_EL1_IRGN0_FIELD  (8)

-#define TCR_EL1_ORGN0_FIELD  (10)

-#define TCR_EL1_SH0_FIELD    (12)

-#define TCR_EL1_TG0_FIELD    (14)

-#define TCR_EL1_T1SZ_FIELD   (16)

-#define TCR_EL1_A1_FIELD     (22)

-#define TCR_EL1_EPD1_FIELD   (23)

-#define TCR_EL1_IRGN1_FIELD  (24)

-#define TCR_EL1_ORGN1_FIELD  (26)

-#define TCR_EL1_SH1_FIELD    (28)

-#define TCR_EL1_TG1_FIELD    (30)

-#define TCR_EL1_IPS_FIELD    (32)

-#define TCR_EL1_AS_FIELD     (36)

-#define TCR_EL1_TBI0_FIELD   (37)

-#define TCR_EL1_TBI1_FIELD   (38)

-#define TCR_EL1_T0SZ_MASK    (0x1FUL << TCR_EL1_T0SZ_FIELD)

-#define TCR_EL1_EPD0_MASK    (0x01UL << TCR_EL1_EPD0_FIELD)

-#define TCR_EL1_IRGN0_MASK   (0x03UL << TCR_EL1_IRGN0_FIELD)

-#define TCR_EL1_ORGN0_MASK   (0x03UL << TCR_EL1_ORGN0_FIELD)

-#define TCR_EL1_SH0_MASK     (0x03UL << TCR_EL1_SH0_FIELD)

-#define TCR_EL1_TG0_MASK     (0x01UL << TCR_EL1_TG0_FIELD)

-#define TCR_EL1_T1SZ_MASK    (0x1FUL << TCR_EL1_T1SZ_FIELD)

-#define TCR_EL1_A1_MASK      (0x01UL << TCR_EL1_A1_FIELD)

-#define TCR_EL1_EPD1_MASK    (0x01UL << TCR_EL1_EPD1_FIELD)

-#define TCR_EL1_IRGN1_MASK   (0x03UL << TCR_EL1_IRGN1_FIELD)

-#define TCR_EL1_ORGN1_MASK   (0x03UL << TCR_EL1_ORGN1_FIELD)

-#define TCR_EL1_SH1_MASK     (0x03UL << TCR_EL1_SH1_FIELD)

-#define TCR_EL1_TG1_MASK     (0x01UL << TCR_EL1_TG1_FIELD)

-#define TCR_EL1_IPS_MASK     (0x07UL << TCR_EL1_IPS_FIELD)

-#define TCR_EL1_AS_MASK      (0x01UL << TCR_EL1_AS_FIELD)

-#define TCR_EL1_TBI0_MASK    (0x01UL << TCR_EL1_TBI0_FIELD)

-#define TCR_EL1_TBI1_MASK    (0x01UL << TCR_EL1_TBI1_FIELD)

-

-#define TCR_EL23_T0SZ_FIELD   (0)

-#define TCR_EL23_IRGN0_FIELD  (8)

-#define TCR_EL23_ORGN0_FIELD  (10)

-#define TCR_EL23_SH0_FIELD    (12)

-#define TCR_EL23_TG0_FIELD    (14)

-#define TCR_EL23_PS_FIELD     (16)

-#define TCR_EL23_T0SZ_MASK    (0x1FUL << TCR_EL23_T0SZ_FIELD)

-#define TCR_EL23_IRGN0_MASK   (0x03UL << TCR_EL23_IRGN0_FIELD)

-#define TCR_EL23_ORGN0_MASK   (0x03UL << TCR_EL23_ORGN0_FIELD)

-#define TCR_EL23_SH0_MASK     (0x03UL << TCR_EL23_SH0_FIELD)

-#define TCR_EL23_TG0_MASK     (0x01UL << TCR_EL23_TG0_FIELD)

-#define TCR_EL23_PS_MASK      (0x07UL << TCR_EL23_PS_FIELD)

-

-#define TCR_RGN_OUTER_NON_CACHEABLE        (0x0UL << 10)

-#define TCR_RGN_OUTER_WRITE_BACK_ALLOC     (0x1UL << 10)

-#define TCR_RGN_OUTER_WRITE_THROUGH        (0x2UL << 10)

-#define TCR_RGN_OUTER_WRITE_BACK_NO_ALLOC  (0x3UL << 10)

-

-#define TCR_RGN_INNER_NON_CACHEABLE        (0x0UL << 8)

-#define TCR_RGN_INNER_WRITE_BACK_ALLOC     (0x1UL << 8)

-#define TCR_RGN_INNER_WRITE_THROUGH        (0x2UL << 8)

-#define TCR_RGN_INNER_WRITE_BACK_NO_ALLOC  (0x3UL << 8)

-

-#define TCR_SH_NON_SHAREABLE    (0x0UL << 12)

-#define TCR_SH_OUTER_SHAREABLE  (0x2UL << 12)

-#define TCR_SH_INNER_SHAREABLE  (0x3UL << 12)

-

-#define TCR_PASZ_32BITS_4GB    (0x0UL)

-#define TCR_PASZ_36BITS_64GB   (0x1UL)

-#define TCR_PASZ_40BITS_1TB    (0x2UL)

-#define TCR_PASZ_42BITS_4TB    (0x3UL)

-#define TCR_PASZ_44BITS_16TB   (0x4UL)

-#define TCR_PASZ_48BITS_256TB  (0x5UL)

-

-// The value written to the T*SZ fields are defined as 2^(64-T*SZ). So a 39Bit

-// Virtual address range for 512GB of virtual space sets T*SZ to 25

-#define INPUT_ADDRESS_SIZE_TO_TXSZ(a)  (64 - a)

-

-// Uses LPAE Page Table format

-

-#endif // AARCH64_MMU_H_

diff --git a/ArmPkg/Library/ArmExceptionLib/AArch64/AArch64Exception.c b/ArmPkg/Library/ArmExceptionLib/AArch64/AArch64Exception.c
index ef6a132..b0c2e39 100644
--- a/ArmPkg/Library/ArmExceptionLib/AArch64/AArch64Exception.c
+++ b/ArmPkg/Library/ArmExceptionLib/AArch64/AArch64Exception.c
@@ -10,7 +10,7 @@
 

 #include <Uefi.h>

 

-#include <Chipset/AArch64.h>

+#include <AArch64/AArch64.h>

 #include <Library/MemoryAllocationLib.h>

 #include <Protocol/DebugSupport.h> // for MAX_AARCH64_EXCEPTION

 

diff --git a/ArmPkg/Library/ArmExceptionLib/AArch64/ExceptionSupport.S b/ArmPkg/Library/ArmExceptionLib/AArch64/ExceptionSupport.S
index cd9437b..f5cbc2e 100644
--- a/ArmPkg/Library/ArmExceptionLib/AArch64/ExceptionSupport.S
+++ b/ArmPkg/Library/ArmExceptionLib/AArch64/ExceptionSupport.S
@@ -7,7 +7,7 @@
 //

 //------------------------------------------------------------------------------

 

-#include <Chipset/AArch64.h>

+#include <AArch64/AArch64.h>

 #include <Library/PcdLib.h>

 #include <AsmMacroIoLibV8.h>

 #include <Protocol/DebugSupport.h> // for exception type definitions

diff --git a/ArmPkg/Library/ArmLib/AArch64/AArch64Lib.c b/ArmPkg/Library/ArmLib/AArch64/AArch64Lib.c
index 8728546..6739f5c 100644
--- a/ArmPkg/Library/ArmLib/AArch64/AArch64Lib.c
+++ b/ArmPkg/Library/ArmLib/AArch64/AArch64Lib.c
@@ -13,7 +13,7 @@
 #include <Library/ArmLib.h>

 #include <Library/DebugLib.h>

 

-#include <Chipset/AArch64.h>

+#include <AArch64/AArch64.h>

 

 #include "AArch64Lib.h"

 #include "ArmLibPrivate.h"

diff --git a/ArmPkg/Library/ArmLib/AArch64/AArch64Support.S b/ArmPkg/Library/ArmLib/AArch64/AArch64Support.S
index a7111e5..177d10e 100644
--- a/ArmPkg/Library/ArmLib/AArch64/AArch64Support.S
+++ b/ArmPkg/Library/ArmLib/AArch64/AArch64Support.S
@@ -9,7 +9,7 @@
 #

 #------------------------------------------------------------------------------

 

-#include <Chipset/AArch64.h>

+#include <AArch64/AArch64.h>

 #include <AsmMacroIoLibV8.h>

 

 .set CTRL_M_BIT,      (1 << 0)

diff --git a/ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibCore.c b/ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibCore.c
index 9d9c623..6a1f3f9 100644
--- a/ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibCore.c
+++ b/ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibCore.c
@@ -11,7 +11,7 @@
 

 #include <Uefi.h>

 #include <Pi/PiMultiPhase.h>

-#include <Chipset/AArch64.h>

+#include <AArch64/AArch64.h>

 #include <Library/BaseMemoryLib.h>

 #include <Library/CacheMaintenanceLib.h>

 #include <Library/MemoryAllocationLib.h>