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| author | oliviermartin <oliviermartin@6f19259b-4bc3-4df7-8a09-765794883524> | 2013-04-14 09:27:33 +0000 |
|---|---|---|
| committer | oliviermartin <oliviermartin@6f19259b-4bc3-4df7-8a09-765794883524> | 2013-04-14 09:27:33 +0000 |
| commit | 81742bb085522dc9120af1b7cc1a1dc959afa7b9 (patch) | |
| tree | 9a371a4af0cf093b2f34b6a68f81e8118ec4362c /ArmPkg | |
| parent | 5ab765a7ad42933b4ea51a1f9593c37f7b32e6d7 (diff) | |
| download | edk2-81742bb085522dc9120af1b7cc1a1dc959afa7b9.zip edk2-81742bb085522dc9120af1b7cc1a1dc959afa7b9.tar.gz edk2-81742bb085522dc9120af1b7cc1a1dc959afa7b9.tar.bz2 | |
ArmPkg/PL390Gic: Do not try to clear spurious interrupts.
If we have a pending spurious interrupt we should not try to clear it,
just ignore.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Olivier Martin <olivier.martin@arm.com>
git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@14265 6f19259b-4bc3-4df7-8a09-765794883524
Diffstat (limited to 'ArmPkg')
| -rw-r--r-- | ArmPkg/Drivers/PL390Gic/PL390GicSec.c | 13 |
1 files changed, 7 insertions, 6 deletions
diff --git a/ArmPkg/Drivers/PL390Gic/PL390GicSec.c b/ArmPkg/Drivers/PL390Gic/PL390GicSec.c index e47e23d..6244575 100644 --- a/ArmPkg/Drivers/PL390Gic/PL390GicSec.c +++ b/ArmPkg/Drivers/PL390Gic/PL390GicSec.c @@ -39,14 +39,15 @@ ArmGicSetupNonSecure ( // Set priority Mask so that no interrupts get through to CPU
MmioWrite32 (GicInterruptInterfaceBase + ARM_GIC_ICCPMR, 0);
- // Check if there are any pending interrupts
- //TODO: could be extended to take Peripheral interrupts into consideration, but at the moment only SGI's are taken into consideration.
- while(0 != (MmioRead32 (GicDistributorBase + ARM_GIC_ICDICPR) & 0xF)) {
- // Some of the SGI's are still pending, read Ack register and send End of Interrupt Signal
- InterruptId = MmioRead32 (GicInterruptInterfaceBase + ARM_GIC_ICCIAR);
+ InterruptId = MmioRead32 (GicInterruptInterfaceBase + ARM_GIC_ICCIAR);
- // Write to End of interrupt signal
+ // Only try to clear valid interrupts. Ignore spurious interrupts.
+ while ((InterruptId & 0x3FF) < ArmGicGetMaxNumInterrupts (GicDistributorBase)) {
+ // Some of the SGI's are still pending, read Ack register and send End of Interrupt Signal
MmioWrite32 (GicInterruptInterfaceBase + ARM_GIC_ICCEIOR, InterruptId);
+
+ // Next
+ InterruptId = MmioRead32 (GicInterruptInterfaceBase + ARM_GIC_ICCIAR);
}
// Only the primary core should set the Non Secure bit to the SPIs (Shared Peripheral Interrupt).
|