ArmPkg/ArmLib: remove unused ARM9 support

The ARM9 ArmLib implementation is not referenced anywhere in the
tree, and unlikely to be useful going forward, considering that
ARM9 outdates even ARMv6. So remove it.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>

git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18750 6f19259b-4bc3-4df7-8a09-765794883524

7 files changed, 0 insertions, 762 deletions

diff --git a/ArmPkg/Include/Chipset/ARM926EJ-S.h b/ArmPkg/Include/Chipset/ARM926EJ-S.h
deleted file mode 100644
index 4ef1103..0000000
--- a/ArmPkg/Include/Chipset/ARM926EJ-S.h
+++ /dev/null
@@ -1,71 +0,0 @@
-/** @file

-

-  Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>

-

-  This program and the accompanying materials

-  are licensed and made available under the terms and conditions of the BSD License

-  which accompanies this distribution.  The full text of the license may be found at

-  http://opensource.org/licenses/bsd-license.php

-

-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,

-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.

-

-**/

-

-#ifndef __ARM926EJ_S_H__

-#define __ARM926EJ_S_H__

-

-// Domain Access Control Register

-#define DOMAIN_ACCESS_CONTROL_MASK(a)     (3UL << (2 * (a)))

-#define DOMAIN_ACCESS_CONTROL_NONE(a)     (0UL << (2 * (a)))

-#define DOMAIN_ACCESS_CONTROL_CLIENT(a)   (1UL << (2 * (a)))

-#define DOMAIN_ACCESS_CONTROL_RESERVED(a) (2UL << (2 * (a)))

-#define DOMAIN_ACCESS_CONTROL_MANAGER(a)  (3UL << (2 * (a)))

-

-#define TRANSLATION_TABLE_SIZE            (16 * 1024)

-#define TRANSLATION_TABLE_ALIGNMENT       (16 * 1024)

-#define TRANSLATION_TABLE_ALIGNMENT_MASK  (TRANSLATION_TABLE_ALIGNMENT - 1)

-

-#define TRANSLATION_TABLE_ENTRY_FOR_VIRTUAL_ADDRESS(table, address) ((UINT32 *)(table) + (((UINTN)(address)) >> 20))

-

-// Translation table descriptor types

-#define TT_DESCRIPTOR_TYPE_MASK     (3UL << 0)

-#define TT_DESCRIPTOR_TYPE_FAULT    (0UL << 0)

-#define TT_DESCRIPTOR_TYPE_COARSE   ((1UL << 0) | (1UL << 4))

-#define TT_DESCRIPTOR_TYPE_SECTION  ((2UL << 0) | (1UL << 4))

-#define TT_DESCRIPTOR_TYPE_FINE     ((3UL << 0) | (1UL << 4))

-

-// Section descriptor definitions

-#define TT_DESCRIPTOR_SECTION_SIZE                              (0x00100000)

-

-#define TT_DESCRIPTOR_SECTION_CACHE_POLICY_MASK                 (3UL <<  2)

-#define TT_DESCRIPTOR_SECTION_CACHE_POLICY_UNCACHED_UNBUFFERED  (0UL <<  2)

-#define TT_DESCRIPTOR_SECTION_CACHE_POLICY_UNCACHED_BUFFERED    (1UL <<  2)

-#define TT_DESCRIPTOR_SECTION_CACHE_POLICY_WRITE_THROUGH        (2UL <<  2)

-#define TT_DESCRIPTOR_SECTION_CACHE_POLICY_WRITE_BACK           (3UL <<  2)

-

-#define TT_DESCRIPTOR_SECTION_ACCESS_PERMISSION_MASK            (3UL << 10)

-#define TT_DESCRIPTOR_SECTION_ACCESS_PERMISSION_NONE            (1UL << 10)

-#define TT_DESCRIPTOR_SECTION_ACCESS_PERMISSION_READ_ONLY       (2UL << 10)

-#define TT_DESCRIPTOR_SECTION_ACCESS_PERMISSION_READ_WRITE      (3UL << 10)

-

-#define TT_DESCRIPTOR_SECTION_DOMAIN_MASK                       (0x0FUL << 5)

-#define TT_DESCRIPTOR_SECTION_DOMAIN(a)                         (((a) & 0xF) << 5)

-

-#define TT_DESCRIPTOR_SECTION_BASE_ADDRESS_MASK                 (0xFFF00000)

-#define TT_DESCRIPTOR_SECTION_BASE_ADDRESS(a)                   (a & TT_DESCRIPTOR_SECTION_BASE_ADDRESS_MASK)

-

-#define TT_DESCRIPTOR_SECTION_WRITE_BACK          (TT_DESCRIPTOR_SECTION_ACCESS_PERMISSION_READ_WRITE | \

-                                                   TT_DESCRIPTOR_SECTION_DOMAIN(0)                    | \

-                                                   TT_DESCRIPTOR_SECTION_CACHE_POLICY_WRITE_BACK      | \

-                                                   TT_DESCRIPTOR_TYPE_SECTION)

-#define TT_DESCRIPTOR_SECTION_WRITE_THROUGH       (TT_DESCRIPTOR_SECTION_ACCESS_PERMISSION_READ_WRITE | \

-                                                   TT_DESCRIPTOR_SECTION_DOMAIN(0)                    | \

-                                                   TT_DESCRIPTOR_SECTION_CACHE_POLICY_WRITE_THROUGH   | \

-                                                   TT_DESCRIPTOR_TYPE_SECTION)

-#define TT_DESCRIPTOR_SECTION_UNCACHED_UNBUFFERED (TT_DESCRIPTOR_SECTION_ACCESS_PERMISSION_READ_WRITE     | \

-                                                   TT_DESCRIPTOR_SECTION_DOMAIN(0)                        | \

-                                                   TT_DESCRIPTOR_SECTION_CACHE_POLICY_UNCACHED_UNBUFFERED | \

-                                                   TT_DESCRIPTOR_TYPE_SECTION)

-

-#endif // __ARM926EJ_S_H__

diff --git a/ArmPkg/Library/ArmLib/Arm9/Arm9ArmLib.inf b/ArmPkg/Library/ArmLib/Arm9/Arm9ArmLib.inf
deleted file mode 100644
index e8aa056..0000000
--- a/ArmPkg/Library/ArmLib/Arm9/Arm9ArmLib.inf
+++ /dev/null
@@ -1,43 +0,0 @@
-#/** @file

-# Semihosting  serail port lib

-#

-# Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>

-#

-#  This program and the accompanying materials

-#  are licensed and made available under the terms and conditions of the BSD License

-#  which accompanies this distribution. The full text of the license may be found at

-#  http://opensource.org/licenses/bsd-license.php

-#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,

-#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.

-#

-#

-#**/

-

-[Defines]

-  INF_VERSION                    = 0x00010005

-  BASE_NAME                      = Arm9ArmLib

-  FILE_GUID                      = 375D70D3-91E0-4374-A540-68BD959EB184

-  MODULE_TYPE                    = DXE_DRIVER

-  VERSION_STRING                 = 1.0

-  LIBRARY_CLASS                  = ArmLib

-

-[Sources.common]

-  ../Common/Arm/ArmLibSupport.S    | GCC

-  ../Common/Arm/ArmLibSupport.asm  | RVCT

-  ../Common/ArmLib.c

-

-  Arm9Support.S    | GCC

-  Arm9Support.asm  | RVCT

-

-  Arm9Lib.c

-  Arm9CacheInformation.c

-

-[Packages]

-  ArmPkg/ArmPkg.dec

-  MdePkg/MdePkg.dec

-

-[LibraryClasses]

-  MemoryAllocationLib

-

-[Protocols]

-  gEfiCpuArchProtocolGuid

diff --git a/ArmPkg/Library/ArmLib/Arm9/Arm9ArmLibPrePi.inf b/ArmPkg/Library/ArmLib/Arm9/Arm9ArmLibPrePi.inf
deleted file mode 100644
index 556e3dc..0000000
--- a/ArmPkg/Library/ArmLib/Arm9/Arm9ArmLibPrePi.inf
+++ /dev/null
@@ -1,43 +0,0 @@
-#/** @file

-# Semihosting  serail port lib

-#

-# Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>

-#

-#  This program and the accompanying materials

-#  are licensed and made available under the terms and conditions of the BSD License

-#  which accompanies this distribution. The full text of the license may be found at

-#  http://opensource.org/licenses/bsd-license.php

-#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,

-#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.

-#

-#

-#**/

-

-[Defines]

-  INF_VERSION                    = 0x00010005

-  BASE_NAME                      = Arm9ArmLibPrePi

-  FILE_GUID                      = e9b6011f-ee15-4e59-ab8f-a819a081fa54

-  MODULE_TYPE                    = DXE_DRIVER

-  VERSION_STRING                 = 1.0

-  LIBRARY_CLASS                  = ArmLib

-

-[Sources.common]

-  ../Common/Arm/ArmLibSupport.S    | GCC

-  ../Common/Arm/ArmLibSupport.asm  | RVCT

-  ../Common/ArmLib.c

-

-  Arm9Support.S    | GCC

-  Arm9Support.asm  | RVCT

-

-  Arm9Lib.c

-  Arm9CacheInformation.c

-

-[Packages]

-  ArmPkg/ArmPkg.dec

-  MdePkg/MdePkg.dec

-

-[LibraryClasses]

-  PrePiLib

-

-[Protocols]

-  gEfiCpuArchProtocolGuid

diff --git a/ArmPkg/Library/ArmLib/Arm9/Arm9CacheInformation.c b/ArmPkg/Library/ArmLib/Arm9/Arm9CacheInformation.c
deleted file mode 100644
index f0b5060..0000000
--- a/ArmPkg/Library/ArmLib/Arm9/Arm9CacheInformation.c
+++ /dev/null
@@ -1,165 +0,0 @@
-/** @file

-

-  Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>

-  Copyright (c) 2014, ARM Limited. All rights reserved.

-

-  This program and the accompanying materials

-  are licensed and made available under the terms and conditions of the BSD License

-  which accompanies this distribution.  The full text of the license may be found at

-  http://opensource.org/licenses/bsd-license.php

-

-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,

-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.

-

-**/

-

-#include <Library/ArmLib.h>

-#include "ArmLibPrivate.h"

-

-ARM_CACHE_TYPE

-EFIAPI

-ArmCacheType (

-  VOID

-  )

-{

-  switch (CACHE_TYPE (ArmCacheInfo ()))

-  {

-    case CACHE_TYPE_WRITE_BACK: return ARM_CACHE_TYPE_WRITE_BACK;

-    default:                    return ARM_CACHE_TYPE_UNKNOWN;

-  }

-}

-

-ARM_CACHE_ARCHITECTURE

-EFIAPI

-ArmCacheArchitecture (

-  VOID

-  )

-{

-  switch (CACHE_ARCHITECTURE (ArmCacheInfo ()))

-  {

-    case CACHE_ARCHITECTURE_UNIFIED:  return ARM_CACHE_ARCHITECTURE_UNIFIED;

-    case CACHE_ARCHITECTURE_SEPARATE: return ARM_CACHE_ARCHITECTURE_SEPARATE;

-    default:                          return ARM_CACHE_ARCHITECTURE_UNKNOWN;

-  }

-}

-

-BOOLEAN

-EFIAPI

-ArmDataCachePresent (

-  VOID

-  )

-{

-  switch (DATA_CACHE_PRESENT (ArmCacheInfo ()))

-  {

-    case CACHE_PRESENT:     return TRUE;

-    case CACHE_NOT_PRESENT: return FALSE;

-    default:                return FALSE;

-  }

-}

-

-UINTN

-EFIAPI

-ArmDataCacheSize (

-  VOID

-  )

-{

-  switch (DATA_CACHE_SIZE (ArmCacheInfo ()))

-  {

-    case CACHE_SIZE_4_KB:   return   4 * 1024;

-    case CACHE_SIZE_8_KB:   return   8 * 1024;

-    case CACHE_SIZE_16_KB:  return  16 * 1024;

-    case CACHE_SIZE_32_KB:  return  32 * 1024;

-    case CACHE_SIZE_64_KB:  return  64 * 1024;

-    case CACHE_SIZE_128_KB: return 128 * 1024;

-    default:                return   0;

-  }

-}

-

-UINTN

-EFIAPI

-ArmDataCacheAssociativity (

-  VOID

-  )

-{

-  switch (DATA_CACHE_ASSOCIATIVITY (ArmCacheInfo ()))

-  {

-    case CACHE_ASSOCIATIVITY_4_WAY:   return 4;

-    case CACHE_ASSOCIATIVITY_DIRECT:  return 1;

-    default:                          return 0;

-  }

-}

-

-UINTN

-EFIAPI

-ArmDataCacheLineLength (

-  VOID

-  )

-{

-  switch (DATA_CACHE_LINE_LENGTH (ArmCacheInfo ()))

-  {

-    case CACHE_LINE_LENGTH_32_BYTES: return 32;

-    default:                         return  0;

-  }

-}

-

-BOOLEAN

-EFIAPI

-ArmInstructionCachePresent (

-  VOID

-  )

-{

-  switch (INSTRUCTION_CACHE_PRESENT (ArmCacheInfo ()))

-  {

-    case CACHE_PRESENT:     return TRUE;

-    case CACHE_NOT_PRESENT: return FALSE;

-    default:                return FALSE;

-  }

-}

-

-UINTN

-EFIAPI

-ArmInstructionCacheSize (

-  VOID

-  )

-{

-  switch (INSTRUCTION_CACHE_SIZE (ArmCacheInfo ()))

-  {

-    case CACHE_SIZE_4_KB:   return   4 * 1024;

-    case CACHE_SIZE_8_KB:   return   8 * 1024;

-    case CACHE_SIZE_16_KB:  return  16 * 1024;

-    case CACHE_SIZE_32_KB:  return  32 * 1024;

-    case CACHE_SIZE_64_KB:  return  64 * 1024;

-    case CACHE_SIZE_128_KB: return 128 * 1024;

-    default:                return   0;

-  }

-}

-

-UINTN

-EFIAPI

-ArmInstructionCacheAssociativity (

-  VOID

-  )

-{

-  switch (INSTRUCTION_CACHE_ASSOCIATIVITY (ArmCacheInfo ()))

-  {

-    case CACHE_ASSOCIATIVITY_8_WAY:   return 8;

-    case CACHE_ASSOCIATIVITY_4_WAY:   return 4;

-    case CACHE_ASSOCIATIVITY_DIRECT:  return 1;

-    default:                          return 0;

-  }

-}

-

-UINTN

-EFIAPI

-ArmInstructionCacheLineLength (

-  VOID

-  )

-{

-  switch (INSTRUCTION_CACHE_LINE_LENGTH (ArmCacheInfo ()))

-  {

-    case CACHE_LINE_LENGTH_32_BYTES: return 32;

-    default:                         return  0;

-  }

-}

-

-

diff --git a/ArmPkg/Library/ArmLib/Arm9/Arm9Lib.c b/ArmPkg/Library/ArmLib/Arm9/Arm9Lib.c
deleted file mode 100644
index 7432f7b..0000000
--- a/ArmPkg/Library/ArmLib/Arm9/Arm9Lib.c
+++ /dev/null
@@ -1,134 +0,0 @@
-/** @file

-

-  Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>

-  Copyright (c) 2011 - 2013, ARM Limited. All rights reserved.

-

-  This program and the accompanying materials

-  are licensed and made available under the terms and conditions of the BSD License

-  which accompanies this distribution.  The full text of the license may be found at

-  http://opensource.org/licenses/bsd-license.php

-

-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,

-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.

-

-**/

-

-#include <Chipset/ARM926EJ-S.h>

-#include <Library/ArmLib.h>

-#include <Library/BaseMemoryLib.h>

-#include <Library/MemoryAllocationLib.h>

-#include <Library/DebugLib.h>

-

-VOID

-FillTranslationTable (

-  IN  UINT32                        *TranslationTable,

-  IN  ARM_MEMORY_REGION_DESCRIPTOR  *MemoryRegion

-  )

-{

-  UINT32  *Entry;

-  UINTN   Sections;

-  UINTN   Index;

-  UINT32  Attributes;

-  UINT32  PhysicalBase = MemoryRegion->PhysicalBase;

-

-  switch (MemoryRegion->Attributes) {

-    case ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK:

-      Attributes = TT_DESCRIPTOR_SECTION_WRITE_BACK;

-      break;

-    case ARM_MEMORY_REGION_ATTRIBUTE_WRITE_THROUGH:

-      Attributes = TT_DESCRIPTOR_SECTION_WRITE_THROUGH;

-      break;

-    case ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED:

-      Attributes = TT_DESCRIPTOR_SECTION_UNCACHED_UNBUFFERED;

-      break;

-    case ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_BACK:

-    case ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_THROUGH:

-    case ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_UNCACHED_UNBUFFERED:

-      ASSERT(0); // Trustzone is not supported on ARMv5

-    default:

-      Attributes = TT_DESCRIPTOR_SECTION_UNCACHED_UNBUFFERED;

-      break;

-  }

-

-  Entry    = TRANSLATION_TABLE_ENTRY_FOR_VIRTUAL_ADDRESS(TranslationTable, MemoryRegion->VirtualBase);

-  Sections = MemoryRegion->Length / TT_DESCRIPTOR_SECTION_SIZE;

-

-  // The current code does not support memory region size that is not aligned on TT_DESCRIPTOR_SECTION_SIZE boundary

-  ASSERT (MemoryRegion->Length % TT_DESCRIPTOR_SECTION_SIZE == 0);

-

-  for (Index = 0; Index < Sections; Index++)

-  {

-    *Entry++     =  TT_DESCRIPTOR_SECTION_BASE_ADDRESS(PhysicalBase) | Attributes;

-    PhysicalBase += TT_DESCRIPTOR_SECTION_SIZE;

-  }

-}

-

-RETURN_STATUS

-EFIAPI

-ArmConfigureMmu (

-  IN  ARM_MEMORY_REGION_DESCRIPTOR  *MemoryTable,

-  OUT VOID                         **TranslationTableBase OPTIONAL,

-  OUT UINTN                         *TranslationTableSize OPTIONAL

-  )

-{

-  VOID  *TranslationTable;

-

-  // Allocate pages for translation table.

-  TranslationTable = AllocatePages (EFI_SIZE_TO_PAGES (TRANSLATION_TABLE_SIZE + TRANSLATION_TABLE_ALIGNMENT));

-  if (TranslationTable == NULL) {

-    return RETURN_OUT_OF_RESOURCES;

-  }

-  TranslationTable = (VOID *)(((UINTN)TranslationTable + TRANSLATION_TABLE_ALIGNMENT_MASK) & ~TRANSLATION_TABLE_ALIGNMENT_MASK);

-

-  if (TranslationTableBase != NULL) {

-    *TranslationTableBase = TranslationTable;

-  }

-

-  if (TranslationTableBase != NULL) {

-    *TranslationTableSize = TRANSLATION_TABLE_SIZE;

-  }

-

-  ZeroMem(TranslationTable, TRANSLATION_TABLE_SIZE);

-

-  ArmCleanInvalidateDataCache();

-  ArmInvalidateInstructionCache();

-  ArmInvalidateTlb();

-

-  ArmDisableDataCache();

-  ArmDisableInstructionCache();

-  ArmDisableMmu();

-

-  // Make sure nothing sneaked into the cache

-  ArmCleanInvalidateDataCache();

-  ArmInvalidateInstructionCache();

-

-  while (MemoryTable->Length != 0) {

-    FillTranslationTable(TranslationTable, MemoryTable);

-    MemoryTable++;

-  }

-

-  ArmSetTTBR0(TranslationTable);

-

-  ArmSetDomainAccessControl(DOMAIN_ACCESS_CONTROL_NONE(15) |

-                            DOMAIN_ACCESS_CONTROL_NONE(14) |

-                            DOMAIN_ACCESS_CONTROL_NONE(13) |

-                            DOMAIN_ACCESS_CONTROL_NONE(12) |

-                            DOMAIN_ACCESS_CONTROL_NONE(11) |

-                            DOMAIN_ACCESS_CONTROL_NONE(10) |

-                            DOMAIN_ACCESS_CONTROL_NONE( 9) |

-                            DOMAIN_ACCESS_CONTROL_NONE( 8) |

-                            DOMAIN_ACCESS_CONTROL_NONE( 7) |

-                            DOMAIN_ACCESS_CONTROL_NONE( 6) |

-                            DOMAIN_ACCESS_CONTROL_NONE( 5) |

-                            DOMAIN_ACCESS_CONTROL_NONE( 4) |

-                            DOMAIN_ACCESS_CONTROL_NONE( 3) |

-                            DOMAIN_ACCESS_CONTROL_NONE( 2) |

-                            DOMAIN_ACCESS_CONTROL_NONE( 1) |

-                            DOMAIN_ACCESS_CONTROL_MANAGER(0));

-

-  ArmEnableInstructionCache();

-  ArmEnableDataCache();

-  ArmEnableMmu();

-

-  return RETURN_SUCCESS;

-}

diff --git a/ArmPkg/Library/ArmLib/Arm9/Arm9Support.S b/ArmPkg/Library/ArmLib/Arm9/Arm9Support.S
deleted file mode 100644
index c708d21..0000000
--- a/ArmPkg/Library/ArmLib/Arm9/Arm9Support.S
+++ /dev/null
@@ -1,153 +0,0 @@
-#------------------------------------------------------------------------------

-#

-# Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>

-#

-# This program and the accompanying materials

-# are licensed and made available under the terms and conditions of the BSD License

-# which accompanies this distribution.  The full text of the license may be found at

-# http://opensource.org/licenses/bsd-license.php

-#

-# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,

-# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.

-#

-#------------------------------------------------------------------------------

-

-.text

-.align 2

-GCC_ASM_EXPORT(ArmCleanInvalidateDataCache)

-GCC_ASM_EXPORT(ArmCleanDataCache)

-GCC_ASM_EXPORT(ArmInvalidateDataCache)

-GCC_ASM_EXPORT(ArmInvalidateInstructionCache)

-GCC_ASM_EXPORT(ArmInvalidateDataCacheEntryByMVA)

-GCC_ASM_EXPORT(ArmCleanDataCacheEntryByMVA)

-GCC_ASM_EXPORT(ArmCleanInvalidateDataCacheEntryByMVA)

-GCC_ASM_EXPORT(ArmEnableMmu)

-GCC_ASM_EXPORT(ArmDisableMmu)

-GCC_ASM_EXPORT(ArmMmuEnabled)

-GCC_ASM_EXPORT(ArmEnableDataCache)

-GCC_ASM_EXPORT(ArmDisableDataCache)

-GCC_ASM_EXPORT(ArmEnableInstructionCache)

-GCC_ASM_EXPORT(ArmDisableInstructionCache)

-GCC_ASM_EXPORT(ArmEnableBranchPrediction)

-GCC_ASM_EXPORT(ArmDisableBranchPrediction)

-GCC_ASM_EXPORT(ArmDataMemoryBarrier)

-GCC_ASM_EXPORT(ArmDataSyncronizationBarrier)

-GCC_ASM_EXPORT(ArmInstructionSynchronizationBarrier)

-

-

-.set DC_ON, (1<<2)

-.set IC_ON, (1<<12)

-

-#------------------------------------------------------------------------------

-

-ASM_PFX(ArmInvalidateDataCacheEntryByMVA):

-  mcr     p15, 0, r0, c7, c6, 1   @ invalidate single data cache line

-  bx      lr

-

-ASM_PFX(ArmCleanDataCacheEntryByMVA):

-  mcr     p15, 0, r0, c7, c10, 1  @ clean single data cache line

-  bx      lr

-

-ASM_PFX(ArmCleanInvalidateDataCacheEntryByMVA):

-  mcr     p15, 0, r0, c7, c14, 1  @ clean and invalidate single data cache line

-  bx      lr

-

-ASM_PFX(ArmEnableInstructionCache):

-  ldr    r1,=IC_ON

-  mrc    p15,0,r0,c1,c0,0     @Read control register configuration data

-  orr    r0,r0,r1             @Set I bit

-  mcr    p15,0,r0,c1,c0,0     @Write control register configuration data

-  bx     LR

-

-ASM_PFX(ArmDisableInstructionCache):

-  ldr    r1,=IC_ON

-  mrc    p15,0,r0,c1,c0,0     @Read control register configuration data

-  bic    r0,r0,r1             @Clear I bit.

-  mcr    p15,0,r0,c1,c0,0     @Write control register configuration data

-  bx     LR

-

-ASM_PFX(ArmInvalidateInstructionCache):

-  mov     r0,#0

-  mcr     p15,0,r0,c7,c5,0     @Invalidate entire Instruction cache.

-                         @Also flushes the branch target cache.

-  mov     r0,#0

-  mcr     p15,0,r0,c7,c10,4    @Data write buffer

-  bx      LR

-

-ASM_PFX(ArmEnableMmu):

-  mrc     p15,0,R0,c1,c0,0

-  orr     R0,R0,#1

-  mcr     p15,0,R0,c1,c0,0

-  bx      LR

-

-ASM_PFX(ArmMmuEnabled):

-  mrc     p15,0,R0,c1,c0,0

-  and     R0,R0,#1

-  bx      LR

-

-ASM_PFX(ArmDisableMmu):

-  mrc     p15,0,R0,c1,c0,0

-  bic     R0,R0,#1

-  mcr     p15,0,R0,c1,c0,0

-  mov     R0,#0

-  mcr     p15,0,R0,c7,c10,4     @Drain write buffer

-  bx      LR

-

-ASM_PFX(ArmEnableDataCache):

-  ldr     R1,=DC_ON

-  mrc     p15,0,R0,c1,c0,0      @Read control register configuration data

-  orr     R0,R0,R1              @Set C bit

-  mcr     p15,0,r0,c1,c0,0      @Write control register configuration data

-  bx      LR

-

-ASM_PFX(ArmDisableDataCache):

-  ldr     R1,=DC_ON

-  mrc     p15,0,R0,c1,c0,0      @Read control register configuration data

-  bic     R0,R0,R1              @Clear C bit

-  mcr     p15,0,r0,c1,c0,0      @Write control register configuration data

-  bx      LR

-

-ASM_PFX(ArmCleanDataCache):

-  mrc     p15,0,r15,c7,c10,3

-  bne     ASM_PFX(ArmCleanDataCache)

-  mov     R0,#0

-  mcr     p15,0,R0,c7,c10,4  @Drain write buffer

-  bx      LR

-

-ASM_PFX(ArmInvalidateDataCache):

-  mov     R0,#0

-  mcr     p15,0,R0,c7,c6,0        @Invalidate entire data cache

-  mov     R0,#0

-  mcr     p15,0,R0,c7,c10,4       @Drain write buffer

-  bx      LR

-

-ASM_PFX(ArmCleanInvalidateDataCache):

-  mrc     p15,0,r15,c7,c14,3

-  bne     ASM_PFX(ArmCleanInvalidateDataCache)

-  mov     R0,#0

-  mcr     p15,0,R0,c7,c10,4        @Drain write buffer

-  bx      LR

-

-ASM_PFX(ArmEnableBranchPrediction):

-  bx      LR                      @Branch prediction is not supported.

-

-ASM_PFX(ArmDisableBranchPrediction):

-  bx      LR                      @Branch prediction is not supported.

-

-ASM_PFX(ArmDataMemoryBarrier):

-  mov R0, #0

-  mcr P15, #0, R0, C7, C10, #5    @ check if this is OK?

-  bx      LR

-

-ASM_PFX(ArmDataSyncronizationBarrier):

-  mov R0, #0

-  mcr P15, #0, R0, C7, C10, #4   @ check if this is OK?

-  bx      LR

-

-ASM_PFX(ArmInstructionSynchronizationBarrier):

-  mov R0, #0

-  mcr P15, #0, R0, C7, C5, #4     @ check if this is OK?

-  bx      LR

-

-ASM_FUNCTION_REMOVE_IF_UNREFERENCED

-

diff --git a/ArmPkg/Library/ArmLib/Arm9/Arm9Support.asm b/ArmPkg/Library/ArmLib/Arm9/Arm9Support.asm
deleted file mode 100644
index 4aaa546..0000000
--- a/ArmPkg/Library/ArmLib/Arm9/Arm9Support.asm
+++ /dev/null
@@ -1,153 +0,0 @@
-//------------------------------------------------------------------------------

-//

-// Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>

-//

-// This program and the accompanying materials

-// are licensed and made available under the terms and conditions of the BSD License

-// which accompanies this distribution.  The full text of the license may be found at

-// http://opensource.org/licenses/bsd-license.php

-//

-// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,

-// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.

-//

-//------------------------------------------------------------------------------

-

-    EXPORT  ArmCleanInvalidateDataCache

-    EXPORT  ArmCleanDataCache

-    EXPORT  ArmInvalidateDataCache

-    EXPORT  ArmInvalidateInstructionCache

-    EXPORT  ArmInvalidateDataCacheEntryByMVA

-    EXPORT  ArmCleanDataCacheEntryByMVA

-    EXPORT  ArmCleanInvalidateDataCacheEntryByMVA

-    EXPORT  ArmEnableMmu

-    EXPORT  ArmDisableMmu

-    EXPORT  ArmMmuEnabled

-    EXPORT  ArmEnableDataCache

-    EXPORT  ArmDisableDataCache

-    EXPORT  ArmEnableInstructionCache

-    EXPORT  ArmDisableInstructionCache

-    EXPORT  ArmEnableBranchPrediction

-    EXPORT  ArmDisableBranchPrediction

-    EXPORT  ArmDataMemoryBarrier

-    EXPORT  ArmDataSyncronizationBarrier

-    EXPORT  ArmInstructionSynchronizationBarrier

-

-

-DC_ON       EQU     ( 0x1:SHL:2 )

-IC_ON       EQU     ( 0x1:SHL:12 )

-

-    AREA    ArmCacheLib, CODE, READONLY

-    PRESERVE8

-

-

-ArmInvalidateDataCacheEntryByMVA

-  MCR     p15, 0, r0, c7, c6, 1   ; invalidate single data cache line

-  BX      lr

-

-

-ArmCleanDataCacheEntryByMVA

-  MCR     p15, 0, r0, c7, c10, 1  ; clean single data cache line

-  BX      lr

-

-

-ArmCleanInvalidateDataCacheEntryByMVA

-  MCR     p15, 0, r0, c7, c14, 1  ; clean and invalidate single data cache line

-  BX      lr

-

-ArmEnableInstructionCache

-  LDR     R1,=IC_ON

-  MRC     p15,0,R0,c1,c0,0     ;Read control register configuration data

-  ORR     R0,R0,R1             ;Set I bit

-  MCR     p15,0,r0,c1,c0,0     ;Write control register configuration data

-  BX      LR

-

-ArmDisableInstructionCache

-  LDR     R1,=IC_ON

-  MRC     p15,0,R0,c1,c0,0     ;Read control register configuration data

-  BIC     R0,R0,R1             ;Clear I bit.

-  MCR     p15,0,r0,c1,c0,0     ;Write control register configuration data

-  BX      LR

-

-ArmInvalidateInstructionCache

-  MOV     R0,#0

-  MCR     p15,0,R0,c7,c5,0      ;Invalidate entire instruction cache

-  MOV     R0,#0

-  MCR     p15,0,R0,c7,c10,4     ;Drain write buffer

-  BX      LR

-

-ArmEnableMmu

-  mrc     p15,0,R0,c1,c0,0

-  orr     R0,R0,#1

-  mcr     p15,0,R0,c1,c0,0

-  bx      LR

-

-ArmMmuEnabled

-  mrc     p15,0,R0,c1,c0,0

-  and     R0,R0,#1

-  bx      LR

-

-ArmDisableMmu

-  mrc     p15,0,R0,c1,c0,0

-  bic     R0,R0,#1

-  mcr     p15,0,R0,c1,c0,0

-  mov     R0,#0

-  mcr     p15,0,R0,c7,c10,4     ;Drain write buffer

-  bx      LR

-

-ArmEnableDataCache

-  LDR     R1,=DC_ON

-  MRC     p15,0,R0,c1,c0,0      ;Read control register configuration data

-  ORR     R0,R0,R1              ;Set C bit

-  MCR     p15,0,r0,c1,c0,0      ;Write control register configuration data

-  BX      LR

-

-ArmDisableDataCache

-  LDR     R1,=DC_ON

-  MRC     p15,0,R0,c1,c0,0      ;Read control register configuration data

-  BIC     R0,R0,R1              ;Clear C bit

-  MCR     p15,0,r0,c1,c0,0      ;Write control register configuration data

-  BX      LR

-

-ArmCleanDataCache

-  MRC     p15,0,r15,c7,c10,3

-  BNE     ArmCleanDataCache

-  MOV     R0,#0

-  MCR     p15,0,R0,c7,c10,4      ;Drain write buffer

-  BX      LR

-

-ArmInvalidateDataCache

-  MOV     R0,#0

-  MCR     p15,0,R0,c7,c6,0      ;Invalidate entire data cache

-  MOV     R0,#0

-  MCR     p15,0,R0,c7,c10,4     ;Drain write buffer

-  BX      LR

-

-ArmCleanInvalidateDataCache

-  MRC     p15,0,r15,c7,c14,3

-  BNE     ArmCleanInvalidateDataCache

-  MOV     R0,#0

-  MCR     p15,0,R0,c7,c10,4      ;Drain write buffer

-  BX      LR

-

-ArmEnableBranchPrediction

-  bx      LR                    ;Branch prediction is not supported.

-

-ArmDisableBranchPrediction

-  bx      LR                    ;Branch prediction is not supported.

-

-ASM_PFX(ArmDataMemoryBarrier):

-  mov R0, #0

-  mcr P15, #0, R0, C7, C10, #5  ; Check to see if this is correct

-  bx      LR

-

-ASM_PFX(ArmDataSyncronizationBarrier):

-  mov R0, #0

-  mcr P15, #0, R0, C7, C10, #4 ; Check to see if this is correct

-  bx      LR

-

-ASM_PFX(ArmInstructionSynchronizationBarrier):

-  MOV R0, #0

-  MCR P15, #0, R0, C7, C5, #4 ; Check to see if this is correct

-  bx      LR

-

-    END