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author | Ard Biesheuvel <ard.biesheuvel@linaro.org> | 2016-03-17 08:55:39 +0100 |
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committer | Ard Biesheuvel <ard.biesheuvel@linaro.org> | 2016-03-22 14:39:02 +0100 |
commit | 2187f9a0523c44604a27bbf6563d5c373e73cc31 (patch) | |
tree | b5c0634cc0d5df2373a7052d098a530b4cb70a0a /ArmPkg | |
parent | 02e261c3f8b8aca1221f53e3845275a8a2a82dc8 (diff) | |
download | edk2-2187f9a0523c44604a27bbf6563d5c373e73cc31.zip edk2-2187f9a0523c44604a27bbf6563d5c373e73cc31.tar.gz edk2-2187f9a0523c44604a27bbf6563d5c373e73cc31.tar.bz2 |
ArmPkg/ArmExceptionLib: don't restore ESR and FAR upon exception return
ESR and FAR are populated by the hardware upon exception entry, and
describe the exception, not the interrupted context. So there is no point
in restoring their values before returning from the exception.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
Reviewed-by: Eugene Cohen <eugene@hp.com>
Diffstat (limited to 'ArmPkg')
-rw-r--r-- | ArmPkg/Library/ArmExceptionLib/AArch64/ExceptionSupport.S | 6 |
1 files changed, 0 insertions, 6 deletions
diff --git a/ArmPkg/Library/ArmExceptionLib/AArch64/ExceptionSupport.S b/ArmPkg/Library/ArmExceptionLib/AArch64/ExceptionSupport.S index 3117e71..c7ea061 100644 --- a/ArmPkg/Library/ArmExceptionLib/AArch64/ExceptionSupport.S +++ b/ArmPkg/Library/ArmExceptionLib/AArch64/ExceptionSupport.S @@ -356,18 +356,12 @@ ASM_PFX(CommonExceptionEntry): EL1_OR_EL2_OR_EL3(x6)
1:msr elr_el1, x1 // Exception Link Register
msr spsr_el1,x2 // Saved Processor Status Register 32bit
- msr esr_el1, x4 // EL1 Exception syndrome register 32bit
- msr far_el1, x5 // EL1 Fault Address Register
b 4f
2:msr elr_el2, x1 // Exception Link Register
msr spsr_el2,x2 // Saved Processor Status Register 32bit
- msr esr_el2, x4 // EL2 Exception syndrome register 32bit
- msr far_el2, x5 // EL2 Fault Address Register
b 4f
3:msr elr_el3, x1 // Exception Link Register
msr spsr_el3,x2 // Saved Processor Status Register 32bit
- msr esr_el3, x4 // EL3 Exception syndrome register 32bit
- msr far_el3, x5 // EL3 Fault Address Register
4:msr fpsr, x3 // Floating point Status Register 32bit
// pop all regs and return from exception.
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