ArmPkg: remove cache maintenance by VA operation range size threshold

This removes the range size threshold for virtual address based cache
maintenance instructions that operate on VA ranges to be 'promoted' to
use set/way instructions.

Doing so is unsafe: set/way operations are fundamentally different
from VA operations, and really only suitable for cleaning or invalidating
a cache when turning it on or off.

To quote the ARM ARM (DDI0487A_d G3.4):
"""
Since the set/way instructions are performed only locally, there is no
guarantee of the atomicity of cache maintenance between different PEs,
even if those different PEs are each performing the same cache maintenance
instructions at the same time. Since any cacheable line can be allocated
into the cache at any time, it is possible for [a] cache line to migrate
from an entry in the cache of one PE to the cache of a different PE in a
manner that the cache line avoids being affected by set/way based cache
maintenance. Therefore, ARM strongly discourages the use of set/way
instructions to manage coherency in coherent systems.
"""

Contributed-under: TianoCore Contribution Agreement 1.0
Reviewed-by: Olivier Martin <Olivier.Martin@arm.com>
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>



git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@17176 6f19259b-4bc3-4df7-8a09-765794883524

14 files changed, 11 insertions, 51 deletions

diff --git a/ArmPkg/Library/ArmCacheMaintenanceLib/ArmCacheMaintenanceLib.c b/ArmPkg/Library/ArmCacheMaintenanceLib/ArmCacheMaintenanceLib.c
index 8501e5c..d8e53df 100644
--- a/ArmPkg/Library/ArmCacheMaintenanceLib/ArmCacheMaintenanceLib.c
+++ b/ArmPkg/Library/ArmCacheMaintenanceLib/ArmCacheMaintenanceLib.c
@@ -20,27 +20,20 @@ VOID
 CacheRangeOperation (

   IN  VOID            *Start,

   IN  UINTN           Length,

-  IN  CACHE_OPERATION CacheOperation,

   IN  LINE_OPERATION  LineOperation

   )

 {

   UINTN ArmCacheLineLength         = ArmDataCacheLineLength();

   UINTN ArmCacheLineAlignmentMask  = ArmCacheLineLength - 1;

-  UINTN ArmCacheOperationThreshold = PcdGet32(PcdArmCacheOperationThreshold);

 

-  if ((CacheOperation != NULL) && (Length >= ArmCacheOperationThreshold)) {

-    ArmDrainWriteBuffer ();

-    CacheOperation ();

-  } else {

-    // Align address (rounding down)

-    UINTN AlignedAddress = (UINTN)Start - ((UINTN)Start & ArmCacheLineAlignmentMask);

-    UINTN EndAddress     = (UINTN)Start + Length;

+  // Align address (rounding down)

+  UINTN AlignedAddress = (UINTN)Start - ((UINTN)Start & ArmCacheLineAlignmentMask);

+  UINTN EndAddress     = (UINTN)Start + Length;

 

-    // Perform the line operation on an address in each cache line

-    while (AlignedAddress < EndAddress) {

-      LineOperation(AlignedAddress);

-      AlignedAddress += ArmCacheLineLength;

-    }

+  // Perform the line operation on an address in each cache line

+  while (AlignedAddress < EndAddress) {

+    LineOperation(AlignedAddress);

+    AlignedAddress += ArmCacheLineLength;

   }

 }

 

@@ -70,7 +63,7 @@ InvalidateInstructionCacheRange (
   IN      UINTN                     Length

   )

 {

-  CacheRangeOperation (Address, Length, ArmCleanDataCacheToPoU, ArmCleanDataCacheEntryByMVA);

+  CacheRangeOperation (Address, Length, ArmCleanDataCacheEntryByMVA);

   ArmInvalidateInstructionCache ();

   return Address;

 }

@@ -91,7 +84,7 @@ WriteBackInvalidateDataCacheRange (
   IN      UINTN                     Length

   )

 {

-  CacheRangeOperation(Address, Length, ArmCleanInvalidateDataCache, ArmCleanInvalidateDataCacheEntryByMVA);

+  CacheRangeOperation(Address, Length, ArmCleanInvalidateDataCacheEntryByMVA);

   return Address;

 }

 

@@ -111,7 +104,7 @@ WriteBackDataCacheRange (
   IN      UINTN                     Length

   )

 {

-  CacheRangeOperation(Address, Length, ArmCleanDataCache, ArmCleanDataCacheEntryByMVA);

+  CacheRangeOperation(Address, Length, ArmCleanDataCacheEntryByMVA);

   return Address;

 }

 

@@ -122,6 +115,6 @@ InvalidateDataCacheRange (
   IN      UINTN                     Length

   )

 {

-  CacheRangeOperation(Address, Length, NULL, ArmInvalidateDataCacheEntryByMVA);

+  CacheRangeOperation(Address, Length, ArmInvalidateDataCacheEntryByMVA);

   return Address;

 }

diff --git a/ArmPkg/Library/ArmCacheMaintenanceLib/ArmCacheMaintenanceLib.inf b/ArmPkg/Library/ArmCacheMaintenanceLib/ArmCacheMaintenanceLib.inf
index 5910db0..d519972 100644
--- a/ArmPkg/Library/ArmCacheMaintenanceLib/ArmCacheMaintenanceLib.inf
+++ b/ArmPkg/Library/ArmCacheMaintenanceLib/ArmCacheMaintenanceLib.inf
@@ -31,6 +31,3 @@
 [LibraryClasses]

   ArmLib

   BaseLib

-

-[FixedPcd]

-  gArmTokenSpaceGuid.PcdArmCacheOperationThreshold

diff --git a/ArmPkg/Library/ArmLib/AArch64/AArch64Lib.inf b/ArmPkg/Library/ArmLib/AArch64/AArch64Lib.inf
index e524784..dd585de 100644
--- a/ArmPkg/Library/ArmLib/AArch64/AArch64Lib.inf
+++ b/ArmPkg/Library/ArmLib/AArch64/AArch64Lib.inf
@@ -41,6 +41,3 @@
 

 [Protocols]

   gEfiCpuArchProtocolGuid

-

-[FixedPcd]

-  gArmTokenSpaceGuid.PcdArmCacheOperationThreshold

diff --git a/ArmPkg/Library/ArmLib/AArch64/AArch64LibPrePi.inf b/ArmPkg/Library/ArmLib/AArch64/AArch64LibPrePi.inf
index 3a99e1b..23fbe86 100644
--- a/ArmPkg/Library/ArmLib/AArch64/AArch64LibPrePi.inf
+++ b/ArmPkg/Library/ArmLib/AArch64/AArch64LibPrePi.inf
@@ -43,6 +43,3 @@
 

 [Protocols]

   gEfiCpuArchProtocolGuid

-

-[FixedPcd]

-  gArmTokenSpaceGuid.PcdArmCacheOperationThreshold

diff --git a/ArmPkg/Library/ArmLib/AArch64/AArch64LibSec.inf b/ArmPkg/Library/ArmLib/AArch64/AArch64LibSec.inf
index 57ac694..302c09a 100644
--- a/ArmPkg/Library/ArmLib/AArch64/AArch64LibSec.inf
+++ b/ArmPkg/Library/ArmLib/AArch64/AArch64LibSec.inf
@@ -38,6 +38,3 @@
 

 [Protocols]

   gEfiCpuArchProtocolGuid

-

-[FixedPcd]

-  gArmTokenSpaceGuid.PcdArmCacheOperationThreshold

diff --git a/ArmPkg/Library/ArmLib/Arm11/Arm11Lib.inf b/ArmPkg/Library/ArmLib/Arm11/Arm11Lib.inf
index 32d9299..6ac74d9 100644
--- a/ArmPkg/Library/ArmLib/Arm11/Arm11Lib.inf
+++ b/ArmPkg/Library/ArmLib/Arm11/Arm11Lib.inf
@@ -47,5 +47,4 @@
   gArmTokenSpaceGuid.PcdRelocateVectorTable

 

 [FixedPcd]

-  gArmTokenSpaceGuid.PcdArmCacheOperationThreshold

   gArmTokenSpaceGuid.PcdCpuVectorBaseAddress

diff --git a/ArmPkg/Library/ArmLib/Arm11/Arm11LibPrePi.inf b/ArmPkg/Library/ArmLib/Arm11/Arm11LibPrePi.inf
index 94dd03d..239493d 100644
--- a/ArmPkg/Library/ArmLib/Arm11/Arm11LibPrePi.inf
+++ b/ArmPkg/Library/ArmLib/Arm11/Arm11LibPrePi.inf
@@ -47,5 +47,4 @@
   gArmTokenSpaceGuid.PcdRelocateVectorTable

 

 [FixedPcd]

-  gArmTokenSpaceGuid.PcdArmCacheOperationThreshold

   gArmTokenSpaceGuid.PcdCpuVectorBaseAddress

diff --git a/ArmPkg/Library/ArmLib/Arm11/Arm11LibSec.inf b/ArmPkg/Library/ArmLib/Arm11/Arm11LibSec.inf
index 69763ed..ef3c8f8 100644
--- a/ArmPkg/Library/ArmLib/Arm11/Arm11LibSec.inf
+++ b/ArmPkg/Library/ArmLib/Arm11/Arm11LibSec.inf
@@ -43,5 +43,4 @@
   gArmTokenSpaceGuid.PcdRelocateVectorTable

 

 [FixedPcd]

-  gArmTokenSpaceGuid.PcdArmCacheOperationThreshold

   gArmTokenSpaceGuid.PcdCpuVectorBaseAddress

diff --git a/ArmPkg/Library/ArmLib/Arm9/Arm9ArmLib.inf b/ArmPkg/Library/ArmLib/Arm9/Arm9ArmLib.inf
index 81661b2..e8aa056 100644
--- a/ArmPkg/Library/ArmLib/Arm9/Arm9ArmLib.inf
+++ b/ArmPkg/Library/ArmLib/Arm9/Arm9ArmLib.inf
@@ -41,6 +41,3 @@
 

 [Protocols]

   gEfiCpuArchProtocolGuid

-

-[FixedPcd]

-  gArmTokenSpaceGuid.PcdArmCacheOperationThreshold

diff --git a/ArmPkg/Library/ArmLib/Arm9/Arm9ArmLibPrePi.inf b/ArmPkg/Library/ArmLib/Arm9/Arm9ArmLibPrePi.inf
index 0730487..556e3dc 100644
--- a/ArmPkg/Library/ArmLib/Arm9/Arm9ArmLibPrePi.inf
+++ b/ArmPkg/Library/ArmLib/Arm9/Arm9ArmLibPrePi.inf
@@ -41,6 +41,3 @@
 

 [Protocols]

   gEfiCpuArchProtocolGuid

-

-[FixedPcd]

-  gArmTokenSpaceGuid.PcdArmCacheOperationThreshold

diff --git a/ArmPkg/Library/ArmLib/ArmV7/ArmV7Lib.inf b/ArmPkg/Library/ArmLib/ArmV7/ArmV7Lib.inf
index 55c0ec6..01bdfb6 100644
--- a/ArmPkg/Library/ArmLib/ArmV7/ArmV7Lib.inf
+++ b/ArmPkg/Library/ArmLib/ArmV7/ArmV7Lib.inf
@@ -48,6 +48,3 @@
 

 [Protocols]

   gEfiCpuArchProtocolGuid

-

-[FixedPcd]

-  gArmTokenSpaceGuid.PcdArmCacheOperationThreshold

diff --git a/ArmPkg/Library/ArmLib/ArmV7/ArmV7LibPrePi.inf b/ArmPkg/Library/ArmLib/ArmV7/ArmV7LibPrePi.inf
index bc403d5..ac08106 100644
--- a/ArmPkg/Library/ArmLib/ArmV7/ArmV7LibPrePi.inf
+++ b/ArmPkg/Library/ArmLib/ArmV7/ArmV7LibPrePi.inf
@@ -48,6 +48,3 @@
 

 [Protocols]

   gEfiCpuArchProtocolGuid

-

-[FixedPcd]

-  gArmTokenSpaceGuid.PcdArmCacheOperationThreshold

diff --git a/ArmPkg/Library/ArmLib/ArmV7/ArmV7LibSec.inf b/ArmPkg/Library/ArmLib/ArmV7/ArmV7LibSec.inf
index 4081d1a..a958764 100644
--- a/ArmPkg/Library/ArmLib/ArmV7/ArmV7LibSec.inf
+++ b/ArmPkg/Library/ArmLib/ArmV7/ArmV7LibSec.inf
@@ -42,6 +42,3 @@
 

 [Protocols]

   gEfiCpuArchProtocolGuid

-

-[FixedPcd]

-  gArmTokenSpaceGuid.PcdArmCacheOperationThreshold

diff --git a/ArmPkg/Library/ArmLib/Null/NullArmLib.inf b/ArmPkg/Library/ArmLib/Null/NullArmLib.inf
index 21c374f..36860a7 100644
--- a/ArmPkg/Library/ArmLib/Null/NullArmLib.inf
+++ b/ArmPkg/Library/ArmLib/Null/NullArmLib.inf
@@ -40,6 +40,3 @@
 

 [Protocols]

   gEfiCpuArchProtocolGuid

-

-[FixedPcd]

-  gArmTokenSpaceGuid.PcdArmCacheOperationThreshold