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author | AJFISH <AJFISH@6f19259b-4bc3-4df7-8a09-765794883524> | 2010-01-14 03:25:08 +0000 |
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committer | AJFISH <AJFISH@6f19259b-4bc3-4df7-8a09-765794883524> | 2010-01-14 03:25:08 +0000 |
commit | f659880bfa42ded20a00d3e371c998b42dcdd0fd (patch) | |
tree | 1f5c258cb3169db81493b2b0d43a2bae347d5417 /ArmPkg/Library/ArmCacheMaintenanceLib | |
parent | 66b631f5e0beb4792a0f54c31aab5b08b97dc329 (diff) | |
download | edk2-f659880bfa42ded20a00d3e371c998b42dcdd0fd.zip edk2-f659880bfa42ded20a00d3e371c998b42dcdd0fd.tar.gz edk2-f659880bfa42ded20a00d3e371c998b42dcdd0fd.tar.bz2 |
Added support for L2 (4K) page tables and made the CPU driver change cachability attributes on request. Also got the DebugUncache infrastructure working for the first time. Looks like it works for the simple case. Checking in so we can get more eyes looking at the code.
git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@9734 6f19259b-4bc3-4df7-8a09-765794883524
Diffstat (limited to 'ArmPkg/Library/ArmCacheMaintenanceLib')
-rw-r--r-- | ArmPkg/Library/ArmCacheMaintenanceLib/ArmCacheMaintenanceLib.c | 12 |
1 files changed, 4 insertions, 8 deletions
diff --git a/ArmPkg/Library/ArmCacheMaintenanceLib/ArmCacheMaintenanceLib.c b/ArmPkg/Library/ArmCacheMaintenanceLib/ArmCacheMaintenanceLib.c index 7da6b42..b5754e6 100644 --- a/ArmPkg/Library/ArmCacheMaintenanceLib/ArmCacheMaintenanceLib.c +++ b/ArmPkg/Library/ArmCacheMaintenanceLib/ArmCacheMaintenanceLib.c @@ -27,19 +27,15 @@ CacheRangeOperation ( UINTN ArmCacheLineAlignmentMask = ArmCacheLineLength - 1; UINTN ArmCacheOperationThreshold = PcdGet32(PcdArmCacheOperationThreshold); - if ((CacheOperation != NULL) && (Length >= ArmCacheOperationThreshold)) - { - CacheOperation(); - } - else - { + if ((CacheOperation != NULL) && (Length >= ArmCacheOperationThreshold)) { + CacheOperation (); + } else { // Align address (rounding down) UINTN AlignedAddress = (UINTN)Start - ((UINTN)Start & ArmCacheLineAlignmentMask); UINTN EndAddress = (UINTN)Start + Length; // Perform the line operation on an address in each cache line - while (AlignedAddress < EndAddress) - { + while (AlignedAddress < EndAddress) { LineOperation(AlignedAddress); AlignedAddress += ArmCacheLineLength; } |