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authorEugene Cohen <eugene@hp.com>2015-12-01 18:39:29 +0000
committerabiesheuvel <abiesheuvel@Edk2>2015-12-01 18:39:29 +0000
commitce6aec3ea31270d40ceb64739c5558bee8a09b01 (patch)
treedd20f5daec25e85ca691fb68faacd025ab2a4a26 /ArmPkg/Library/ArmCacheMaintenanceLib
parent911f3dede219d2bb220954768f5e853e0dd976c1 (diff)
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ArmPkg: Convert whole-cache InvalidateInstructionCache to just ASSERT
In SVN 18756 ("disallow whole D-cache maintenance operations") InvalidateInstructionCache was modified to remove the full data cache clean but left the full instruction cache invalidate. The change was made to address issues in the set/way clean methodology but the resulting code could lead someone to a painful debug. If a component called this function, the proper code would not be flushed to the PoU, since the intent of this function is not only to invalidate the I-cache but to provide coherency after code loading / modification. This change simply places an ASSERT(FALSE) in this function to avoid this hazard. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Eugene Cohen <eugene@hp.com> Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@19084 6f19259b-4bc3-4df7-8a09-765794883524
Diffstat (limited to 'ArmPkg/Library/ArmCacheMaintenanceLib')
-rw-r--r--ArmPkg/Library/ArmCacheMaintenanceLib/ArmCacheMaintenanceLib.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/ArmPkg/Library/ArmCacheMaintenanceLib/ArmCacheMaintenanceLib.c b/ArmPkg/Library/ArmCacheMaintenanceLib/ArmCacheMaintenanceLib.c
index 65ba874..feab449 100644
--- a/ArmPkg/Library/ArmCacheMaintenanceLib/ArmCacheMaintenanceLib.c
+++ b/ArmPkg/Library/ArmCacheMaintenanceLib/ArmCacheMaintenanceLib.c
@@ -45,7 +45,7 @@ InvalidateInstructionCache (
VOID
)
{
- ArmInvalidateInstructionCache();
+ ASSERT (FALSE);
}
VOID