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| author | Rebecca Cran <rebecca@nuviainc.com> | 2021-06-14 12:57:49 -0600 |
|---|---|---|
| committer | mergify[bot] <37929162+mergify[bot]@users.noreply.github.com> | 2021-06-18 15:25:57 +0000 |
| commit | a63914d3f603580e5aeceb5edbafe56688210141 (patch) | |
| tree | 632ba952c0958c48b59801697c1262c422055f93 /ArmPkg/Include/Library | |
| parent | 1162ae8297e1fc9871e615cad7d505d639b7ed0c (diff) | |
| download | edk2-a63914d3f603580e5aeceb5edbafe56688210141.zip edk2-a63914d3f603580e5aeceb5edbafe56688210141.tar.gz edk2-a63914d3f603580e5aeceb5edbafe56688210141.tar.bz2 | |
ArmPkg: Move cache defs used in Universal/Smbios into ArmCache.h
Many of the cache definitions in ArmLibPrivate.h are being used outside
of ArmLib, in Universal/Smbios. Move them into ArmCache.h to make them
public, and remove the include of ArmLibPrivate.h from files in
Universal/Smbios.
Signed-off-by: Rebecca Cran <rebecca@nuviainc.com>
Acked-by: Ard Biesheuvel <ardb@kernel.org>
Reviewed-by: Leif Lindholm <leif@nuviainc.com>
Diffstat (limited to 'ArmPkg/Include/Library')
| -rw-r--r-- | ArmPkg/Include/Library/ArmLib.h | 36 |
1 files changed, 32 insertions, 4 deletions
diff --git a/ArmPkg/Include/Library/ArmLib.h b/ArmPkg/Include/Library/ArmLib.h index 5c232d7..79ea755 100644 --- a/ArmPkg/Include/Library/ArmLib.h +++ b/ArmPkg/Include/Library/ArmLib.h @@ -2,7 +2,7 @@ Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
Copyright (c) 2011 - 2016, ARM Ltd. All rights reserved.<BR>
- Copyright (c) 2020, NUVIA Inc. All rights reserved.<BR>
+ Copyright (c) 2020 - 2021, NUVIA Inc. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
@@ -109,9 +109,37 @@ typedef enum { #define GET_MPID(ClusterId, CoreId) (((ClusterId) << 8) | (CoreId))
#define PRIMARY_CORE_ID (PcdGet32(PcdArmPrimaryCore) & ARM_CORE_MASK)
-// The ARM Architecture Reference Manual for ARMv8-A defines up
-// to 7 levels of cache, L1 through L7.
-#define MAX_ARM_CACHE_LEVEL 7
+/** Reads the CCSIDR register for the specified cache.
+
+ @param CSSELR The CSSELR cache selection register value.
+
+ @return The contents of the CCSIDR_EL1 register for the specified cache, when in AARCH64 mode.
+ Returns the contents of the CCSIDR register in AARCH32 mode.
+**/
+UINTN
+ReadCCSIDR (
+ IN UINT32 CSSELR
+ );
+
+/** Reads the CCSIDR2 for the specified cache.
+
+ @param CSSELR The CSSELR cache selection register value
+
+ @return The contents of the CCSIDR2 register for the specified cache.
+**/
+UINT32
+ReadCCSIDR2 (
+ IN UINT32 CSSELR
+ );
+
+/** Reads the Cache Level ID (CLIDR) register.
+
+ @return The contents of the CLIDR_EL1 register.
+**/
+UINT32
+ReadCLIDR (
+ VOID
+ );
UINTN
EFIAPI
|