Added support for L2 (4K) page tables and made the CPU driver change cachability attributes on request. Also got the DebugUncache infrastructure working for the first time. Looks like it works for the simple case. Checking in so we can get more eyes looking at the code.

git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@9734 6f19259b-4bc3-4df7-8a09-765794883524

1 files changed, 100 insertions, 13 deletions

diff --git a/ArmPkg/Drivers/CpuDxe/CpuDxe.c b/ArmPkg/Drivers/CpuDxe/CpuDxe.c
index d3f0ff5..a4ac97c 100644
--- a/ArmPkg/Drivers/CpuDxe/CpuDxe.c
+++ b/ArmPkg/Drivers/CpuDxe/CpuDxe.c
@@ -16,6 +16,34 @@
 

 BOOLEAN mInterruptState   = FALSE;

 

+

+/**

+  This function flushes the range of addresses from Start to Start+Length 

+  from the processor's data cache. If Start is not aligned to a cache line 

+  boundary, then the bytes before Start to the preceding cache line boundary 

+  are also flushed. If Start+Length is not aligned to a cache line boundary, 

+  then the bytes past Start+Length to the end of the next cache line boundary 

+  are also flushed. The FlushType of EfiCpuFlushTypeWriteBackInvalidate must be 

+  supported. If the data cache is fully coherent with all DMA operations, then 

+  this function can just return EFI_SUCCESS. If the processor does not support 

+  flushing a range of the data cache, then the entire data cache can be flushed.

+

+  @param  This             The EFI_CPU_ARCH_PROTOCOL instance.

+  @param  Start            The beginning physical address to flush from the processor's data

+                           cache.

+  @param  Length           The number of bytes to flush from the processor's data cache. This

+                           function may flush more bytes than Length specifies depending upon

+                           the granularity of the flush operation that the processor supports.

+  @param  FlushType        Specifies the type of flush operation to perform.

+

+  @retval EFI_SUCCESS           The address range from Start to Start+Length was flushed from

+                                the processor's data cache.

+  @retval EFI_UNSUPPORTEDT      The processor does not support the cache flush type specified

+                                by FlushType.

+  @retval EFI_DEVICE_ERROR      The address range from Start to Start+Length could not be flushed

+                                from the processor's data cache.

+

+**/

 EFI_STATUS

 EFIAPI

 CpuFlushCpuDataCache (

@@ -25,6 +53,8 @@ CpuFlushCpuDataCache (
   IN EFI_CPU_FLUSH_TYPE              FlushType

   )

 {

+  DEBUG ((EFI_D_ERROR, "CpuFlushCpuDataCache (%lx, %lx, %x)\n", Start, Length, FlushType));

+

   switch (FlushType) {

     case EfiCpuFlushTypeWriteBack:

       WriteBackDataCacheRange ((VOID *)(UINTN)Start, (UINTN)Length);

@@ -42,6 +72,16 @@ CpuFlushCpuDataCache (
   return EFI_SUCCESS;

 }

 

+

+/**

+  This function enables interrupt processing by the processor. 

+

+  @param  This             The EFI_CPU_ARCH_PROTOCOL instance.

+

+  @retval EFI_SUCCESS           Interrupts are enabled on the processor.

+  @retval EFI_DEVICE_ERROR      Interrupts could not be enabled on the processor.

+

+**/

 EFI_STATUS

 EFIAPI

 CpuEnableInterrupt (

@@ -55,6 +95,15 @@ CpuEnableInterrupt (
 }

 

 

+/**

+  This function disables interrupt processing by the processor.

+

+  @param  This             The EFI_CPU_ARCH_PROTOCOL instance.

+

+  @retval EFI_SUCCESS           Interrupts are disabled on the processor.

+  @retval EFI_DEVICE_ERROR      Interrupts could not be disabled on the processor.

+

+**/

 EFI_STATUS

 EFIAPI

 CpuDisableInterrupt (

@@ -67,6 +116,20 @@ CpuDisableInterrupt (
   return EFI_SUCCESS;

 }

 

+

+/**

+  This function retrieves the processor's current interrupt state a returns it in 

+  State. If interrupts are currently enabled, then TRUE is returned. If interrupts 

+  are currently disabled, then FALSE is returned.

+

+  @param  This             The EFI_CPU_ARCH_PROTOCOL instance.

+  @param  State            A pointer to the processor's current interrupt state. Set to TRUE if

+                           interrupts are enabled and FALSE if interrupts are disabled.

+

+  @retval EFI_SUCCESS           The processor's current interrupt state was returned in State.

+  @retval EFI_INVALID_PARAMETER State is NULL.

+

+**/

 EFI_STATUS

 EFIAPI

 CpuGetInterruptState (

@@ -82,6 +145,23 @@ CpuGetInterruptState (
   return EFI_SUCCESS;

 }

 

+

+/**

+  This function generates an INIT on the processor. If this function succeeds, then the

+  processor will be reset, and control will not be returned to the caller. If InitType is 

+  not supported by this processor, or the processor cannot programmatically generate an 

+  INIT without help from external hardware, then EFI_UNSUPPORTED is returned. If an error 

+  occurs attempting to generate an INIT, then EFI_DEVICE_ERROR is returned.

+

+  @param  This             The EFI_CPU_ARCH_PROTOCOL instance.

+  @param  InitType         The type of processor INIT to perform.

+

+  @retval EFI_SUCCESS           The processor INIT was performed. This return code should never be seen.

+  @retval EFI_UNSUPPORTED       The processor INIT operation specified by InitType is not supported

+                                by this processor.

+  @retval EFI_DEVICE_ERROR      The processor INIT failed.

+

+**/

 EFI_STATUS

 EFIAPI

 CpuInit (

@@ -115,17 +195,6 @@ CpuGetTimerValue (
   return EFI_UNSUPPORTED;

 }

 

-EFI_STATUS

-EFIAPI

-CpuSetMemoryAttributes (

-  IN EFI_CPU_ARCH_PROTOCOL     *This,

-  IN EFI_PHYSICAL_ADDRESS      BaseAddress,

-  IN UINT64                    Length,

-  IN UINT64                    Attributes

-  )

-{

-  return EFI_UNSUPPORTED;

-}

 

 //

 // Globals used to initialize the protocol

@@ -149,8 +218,26 @@ CpuDxeInitialize (
   IN EFI_HANDLE         ImageHandle,

   IN EFI_SYSTEM_TABLE   *SystemTable

   )

-{ 

+{

+  EFI_STATUS  Status;

+

   InitializeExceptions (&mCpu);  

-  return gBS->InstallMultipleProtocolInterfaces (&mCpuHandle, &gEfiCpuArchProtocolGuid, &mCpu, NULL);

+  

+  

+  Status = gBS->InstallMultipleProtocolInterfaces (

+                &mCpuHandle, 

+                &gEfiCpuArchProtocolGuid,           &mCpu, 

+                &gVirtualUncachedPagesProtocolGuid, &gVirtualUncachedPages,

+                NULL

+                );

+  

+  //

+  // Make sure GCD and MMU settings match. This API calls gDS->SetMemorySpaceAttributes ()

+  // and that calls EFI_CPU_ARCH_PROTOCOL.SetMemoryAttributes, so this code needs to go

+  // after the protocol is installed

+  //

+  SyncCacheConfig (&mCpu);

+  

+  return Status;

 }