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| author | Jiaxin Wu <jiaxin.wu@intel.com> | 2024-05-31 14:35:27 +0800 |
|---|---|---|
| committer | mergify[bot] <37929162+mergify[bot]@users.noreply.github.com> | 2024-06-14 07:02:37 +0000 |
| commit | af2bbe1b79251f46efaca2ed36860105272dd14f (patch) | |
| tree | 286172f8e617b4beb8c72e91742ad12d3fbbad4a | |
| parent | 712797cf19acd292bf203522a79e40e7e13d268b (diff) | |
| download | edk2-af2bbe1b79251f46efaca2ed36860105272dd14f.zip edk2-af2bbe1b79251f46efaca2ed36860105272dd14f.tar.gz edk2-af2bbe1b79251f46efaca2ed36860105272dd14f.tar.bz2 | |
UefiCpuPkg: Add PcdCpuSmmApSyncTimeout2 PCD
Provide the capability for platform to specifies the 2nd
timeout value in microseconds for the BSP/AP in SMM to wait for
one another to enter SMM.
The added interface can enhance the flexibility of timeout
configuration. In some cases, certain processors may not be
able to enter SMI, and prolonged waiting could lead to
kernel soft/hard lockup. We have now defined two timeouts.
The first timeout can be set to a smaller value to reduce
the waiting period. Processors that are unable to enter SMI
will be woken up through SMIIPL to enter SMI, followed by
a second waiting period. The second timeout can be set to a
larger value to prevent delays in processors entering SMI
case due to the long instruction execution.
Signed-off-by: Jiaxin Wu <jiaxin.wu@intel.com>
Cc: Ray Ni <ray.ni@intel.com>
Cc: Rahul Kumar <rahul1.kumar@intel.com>
Cc: Gerd Hoffmann <kraxel@redhat.com>
| -rw-r--r-- | UefiCpuPkg/UefiCpuPkg.dec | 4 | ||||
| -rw-r--r-- | UefiCpuPkg/UefiCpuPkg.uni | 6 |
2 files changed, 9 insertions, 1 deletions
diff --git a/UefiCpuPkg/UefiCpuPkg.dec b/UefiCpuPkg/UefiCpuPkg.dec index 73bae90..3e91d6c 100644 --- a/UefiCpuPkg/UefiCpuPkg.dec +++ b/UefiCpuPkg/UefiCpuPkg.dec @@ -370,6 +370,10 @@ # @Prompt AP synchronization timeout value in SMM.
gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmApSyncTimeout|1000000|UINT64|0x32132104
+ ## Specifies the 2nd timeout value in microseconds for the BSP/AP in SMM to wait for one another to enter SMM.
+ # @Prompt The 2nd BSP/AP synchronization timeout value in SMM.
+ gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmApSyncTimeout2|1000000|UINT64|0x32132115
+
## Indicates the CPU synchronization method used when processing an SMI.
# 0x00 - Traditional CPU synchronization method.<BR>
# 0x01 - Relaxed CPU synchronization method.<BR>
diff --git a/UefiCpuPkg/UefiCpuPkg.uni b/UefiCpuPkg/UefiCpuPkg.uni index d17bcfd..0637b83 100644 --- a/UefiCpuPkg/UefiCpuPkg.uni +++ b/UefiCpuPkg/UefiCpuPkg.uni @@ -3,7 +3,7 @@ //
// This Package provides UEFI compatible CPU modules and libraries.
//
-// Copyright (c) 2007 - 2020, Intel Corporation. All rights reserved.<BR>
+// Copyright (c) 2007 - 2024, Intel Corporation. All rights reserved.<BR>
//
// SPDX-License-Identifier: BSD-2-Clause-Patent
//
@@ -132,6 +132,10 @@ #string STR_gUefiCpuPkgTokenSpaceGuid_PcdCpuSmmApSyncTimeout_HELP #language en-US "Specifies timeout value in microseconds for the BSP in SMM to wait for all APs to come into SMM."
+#string STR_gUefiCpuPkgTokenSpaceGuid_PcdCpuSmmApSyncTimeout2_PROMPT #language en-US "The 2nd BSP/AP synchronization timeout value in SMM"
+
+#string STR_gUefiCpuPkgTokenSpaceGuid_PcdCpuSmmApSyncTimeout2_HELP #language en-US "Specifies the 2nd timeout value in microseconds for the BSP/AP in SMM to wait for one another to enter SMM."
+
#string STR_gUefiCpuPkgTokenSpaceGuid_PcdCpuSmmCodeAccessCheckEnable_PROMPT #language en-US "SMM Code Access Check"
#string STR_gUefiCpuPkgTokenSpaceGuid_PcdCpuSmmCodeAccessCheckEnable_HELP #language en-US "Enable SMM Code Access Check? If enabled, the SMM handler cannot execute the code outside SMM regions. This PCD is suggested to TRUE in production image.<BR><BR>\n"
|