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authorOlivier Martin <olivier.martin@arm.com>2013-06-19 18:27:55 +0000
committeroliviermartin <oliviermartin@6f19259b-4bc3-4df7-8a09-765794883524>2013-06-19 18:27:55 +0000
commit918c653e1f3fdcb46acadbb65a431391fcd388d2 (patch)
tree48385d7bc346952c5efd7d2e447dda670e738c64
parent2425e1d4fea9f25cfee2497595149b451d91296d (diff)
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ArmPkg/ArmLib: Removed ArmInvalidateTlb when disabling cache as ArmDisableMmu() already does it
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14436 6f19259b-4bc3-4df7-8a09-765794883524
-rw-r--r--ArmPkg/Library/ArmLib/ArmV7/ArmV7Mmu.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/ArmPkg/Library/ArmLib/ArmV7/ArmV7Mmu.c b/ArmPkg/Library/ArmLib/ArmV7/ArmV7Mmu.c
index 6fa770e..7881a9b 100644
--- a/ArmPkg/Library/ArmLib/ArmV7/ArmV7Mmu.c
+++ b/ArmPkg/Library/ArmLib/ArmV7/ArmV7Mmu.c
@@ -222,10 +222,10 @@ ArmConfigureMmu (
ArmCleanInvalidateDataCache ();
ArmInvalidateInstructionCache ();
- ArmInvalidateTlb ();
ArmDisableDataCache ();
ArmDisableInstructionCache();
+ // TLBs are also invalidated when calling ArmDisableMmu()
ArmDisableMmu ();
// Make sure nothing sneaked into the cache