diff options
| author | Jeff Fan <jeff.fan@intel.com> | 2017-02-20 16:17:05 +0800 |
|---|---|---|
| committer | Jeff Fan <jeff.fan@intel.com> | 2017-02-22 15:04:06 +0800 |
| commit | 7537f8c09a63961c5ffb6f584a6bf8210bb2c339 (patch) | |
| tree | bcd1685708961fbfe884e69cb3e051a6886e6749 | |
| parent | 14f92ded906d22274730a92f7801f0ffd84e6193 (diff) | |
| download | edk2-7537f8c09a63961c5ffb6f584a6bf8210bb2c339.zip edk2-7537f8c09a63961c5ffb6f584a6bf8210bb2c339.tar.gz edk2-7537f8c09a63961c5ffb6f584a6bf8210bb2c339.tar.bz2 | |
UefiCpuPkg/CpuDxe: Fix hard code actual TimerPeriod value
Current CpuGetTimerValue() implementation return hard code TimerPeriod value. We
could calculate the actual TimerPeriod value over period of time (100us) at the
first time invoking CpuGetTimerValue() and save the TimerPeriod value into one
global variable to avoid delay at the next CpuGetTimerValue() invoking.
https://bugzilla.tianocore.org/show_bug.cgi?id=382
Cc: Feng Tian <feng.tian@intel.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Feng Tian <feng.tian@Intel.com>
| -rw-r--r-- | UefiCpuPkg/CpuDxe/CpuDxe.c | 24 | ||||
| -rw-r--r-- | UefiCpuPkg/CpuDxe/CpuDxe.h | 3 | ||||
| -rw-r--r-- | UefiCpuPkg/CpuDxe/CpuDxe.inf | 1 |
3 files changed, 25 insertions, 3 deletions
diff --git a/UefiCpuPkg/CpuDxe/CpuDxe.c b/UefiCpuPkg/CpuDxe/CpuDxe.c index c5be1ff..1a5a725 100644 --- a/UefiCpuPkg/CpuDxe/CpuDxe.c +++ b/UefiCpuPkg/CpuDxe/CpuDxe.c @@ -27,6 +27,7 @@ EFI_HANDLE mCpuHandle = NULL; BOOLEAN mIsFlushingGCD;
UINT64 mValidMtrrAddressMask = MTRR_LIB_CACHE_VALID_ADDRESS;
UINT64 mValidMtrrBitsMask = MTRR_LIB_MSR_VALID_MASK;
+UINT64 mTimerPeriod = 0;
FIXED_MTRR mFixedMtrrTable[] = {
{
@@ -297,6 +298,9 @@ CpuGetTimerValue ( OUT UINT64 *TimerPeriod OPTIONAL
)
{
+ UINT64 BeginValue;
+ UINT64 EndValue;
+
if (TimerValue == NULL) {
return EFI_INVALID_PARAMETER;
}
@@ -308,10 +312,26 @@ CpuGetTimerValue ( *TimerValue = AsmReadTsc ();
if (TimerPeriod != NULL) {
+ if (mTimerPeriod == 0) {
+ //
+ // Read time stamp counter before and after delay of 100 microseconds
//
- // BugBug: Hard coded. Don't know how to do this generically
+ BeginValue = AsmReadTsc ();
+ MicroSecondDelay (100);
+ EndValue = AsmReadTsc ();
//
- *TimerPeriod = 1000000000;
+ // Calculate the actual frequency
+ //
+ mTimerPeriod = DivU64x64Remainder (
+ MultU64x32 (
+ 1000 * 1000 * 1000,
+ 100
+ ),
+ EndValue - BeginValue,
+ NULL
+ );
+ }
+ *TimerPeriod = mTimerPeriod;
}
return EFI_SUCCESS;
diff --git a/UefiCpuPkg/CpuDxe/CpuDxe.h b/UefiCpuPkg/CpuDxe/CpuDxe.h index 6dd0ad3..27ad45b 100644 --- a/UefiCpuPkg/CpuDxe/CpuDxe.h +++ b/UefiCpuPkg/CpuDxe/CpuDxe.h @@ -1,7 +1,7 @@ /** @file
CPU DXE Module to produce CPU ARCH Protocol and CPU MP Protocol.
- Copyright (c) 2008 - 2016, Intel Corporation. All rights reserved.<BR>
+ Copyright (c) 2008 - 2017, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
@@ -39,6 +39,7 @@ #include <Library/HobLib.h>
#include <Library/ReportStatusCodeLib.h>
#include <Library/MpInitLib.h>
+#include <Library/TimerLib.h>
#include <Guid/IdleLoopEvent.h>
#include <Guid/VectorHandoffTable.h>
diff --git a/UefiCpuPkg/CpuDxe/CpuDxe.inf b/UefiCpuPkg/CpuDxe/CpuDxe.inf index f61b2c9..e568ceb 100644 --- a/UefiCpuPkg/CpuDxe/CpuDxe.inf +++ b/UefiCpuPkg/CpuDxe/CpuDxe.inf @@ -43,6 +43,7 @@ HobLib
ReportStatusCodeLib
MpInitLib
+ TimerLib
[Sources]
CpuDxe.c
|