diff options
author | Abner Chang <abner.chang@hpe.com> | 2020-04-07 15:45:31 +0800 |
---|---|---|
committer | mergify[bot] <37929162+mergify[bot]@users.noreply.github.com> | 2020-05-07 03:17:15 +0000 |
commit | 1510d6a39157772e9a9cef55dc9d8778a269e969 (patch) | |
tree | c21b00de9e27310db0a03a1a1726b38ad598538a | |
parent | e6956d0052a79dd7d45dd633d8201bce8c34bccd (diff) | |
download | edk2-1510d6a39157772e9a9cef55dc9d8778a269e969.zip edk2-1510d6a39157772e9a9cef55dc9d8778a269e969.tar.gz edk2-1510d6a39157772e9a9cef55dc9d8778a269e969.tar.bz2 |
MdePkg: Add RISC-V RISCV64 binding
Add RISCV64 sections in MdePkg.dec and RISCV64 ProcessorBind.h
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=2672
Signed-off-by: Abner Chang <abner.chang@hpe.com>
Co-authored-by: Gilbert Chen <gilbert.chen@hpe.com>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
Reviewed-by: Zhiguang Liu <zhiguang.liu@intel.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Liming Gao <liming.gao@intel.com>
Cc: Leif Lindholm <leif.lindholm@linaro.org>
Cc: Gilbert Chen <gilbert.chen@hpe.com>
-rw-r--r-- | MdePkg/Include/RiscV64/ProcessorBind.h | 173 | ||||
-rw-r--r-- | MdePkg/MdePkg.dec | 5 | ||||
-rw-r--r-- | MdePkg/MdePkg.dsc | 3 |
3 files changed, 179 insertions, 2 deletions
diff --git a/MdePkg/Include/RiscV64/ProcessorBind.h b/MdePkg/Include/RiscV64/ProcessorBind.h new file mode 100644 index 0000000..2b11f04 --- /dev/null +++ b/MdePkg/Include/RiscV64/ProcessorBind.h @@ -0,0 +1,173 @@ +/** @file
+ Processor or Compiler specific defines and types for RISC-V
+
+ Copyright (c) 2016 - 2020, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef PROCESSOR_BIND_H__
+#define PROCESSOR_BIND_H__
+
+///
+/// Define the processor type so other code can make processor based choices
+///
+#define MDE_CPU_RISCV64
+
+//
+// Make sure we are using the correct packing rules per EFI specification
+//
+#if !defined(__GNUC__)
+#pragma pack()
+#endif
+
+///
+/// 8-byte unsigned value
+///
+typedef unsigned long long UINT64 __attribute__ ((aligned (8)));
+///
+/// 8-byte signed value
+///
+typedef long long INT64 __attribute__ ((aligned (8)));
+///
+/// 4-byte unsigned value
+///
+typedef unsigned int UINT32 __attribute__ ((aligned (4)));
+///
+/// 4-byte signed value
+///
+typedef int INT32 __attribute__ ((aligned (4)));
+///
+/// 2-byte unsigned value
+///
+typedef unsigned short UINT16 __attribute__ ((aligned (2)));
+///
+/// 2-byte Character. Unless otherwise specified all strings are stored in the
+/// UTF-16 encoding format as defined by Unicode 2.1 and ISO/IEC 10646 standards.
+///
+typedef unsigned short CHAR16 __attribute__ ((aligned (2)));
+///
+/// 2-byte signed value
+///
+typedef short INT16 __attribute__ ((aligned (2)));
+///
+/// Logical Boolean. 1-byte value containing 0 for FALSE or a 1 for TRUE. Other
+/// values are undefined.
+///
+typedef unsigned char BOOLEAN;
+///
+/// 1-byte unsigned value
+///
+typedef unsigned char UINT8;
+///
+/// 1-byte Character
+///
+typedef char CHAR8;
+///
+/// 1-byte signed value
+///
+typedef signed char INT8;
+///
+/// Unsigned value of native width. (4 bytes on supported 32-bit processor instructions,
+/// 8 bytes on supported 64-bit processor instructions)
+///
+typedef UINT64 UINTN __attribute__ ((aligned (8)));
+///
+/// Signed value of native width. (4 bytes on supported 32-bit processor instructions,
+/// 8 bytes on supported 64-bit processor instructions)
+///
+typedef INT64 INTN __attribute__ ((aligned (8)));
+
+//
+// Processor specific defines
+//
+
+///
+/// A value of native width with the highest bit set.
+///
+#define MAX_BIT 0x8000000000000000ULL
+///
+/// A value of native width with the two highest bits set.
+///
+#define MAX_2_BITS 0xC000000000000000ULL
+
+///
+/// Maximum legal RV64 address
+///
+#define MAX_ADDRESS 0xFFFFFFFFFFFFFFFFULL
+
+///
+/// Maximum usable address at boot time (48 bits using 4 KB pages in Supervisor mode)
+///
+#define MAX_ALLOC_ADDRESS 0xFFFFFFFFFFFFULL
+
+///
+/// Maximum legal RISC-V INTN and UINTN values.
+///
+#define MAX_INTN ((INTN)0x7FFFFFFFFFFFFFFFULL)
+#define MAX_UINTN ((UINTN)0xFFFFFFFFFFFFFFFFULL)
+
+///
+/// The stack alignment required for RISC-V
+///
+#define CPU_STACK_ALIGNMENT 16
+
+///
+/// Page allocation granularity for RISC-V
+///
+#define DEFAULT_PAGE_ALLOCATION_GRANULARITY (0x1000)
+#define RUNTIME_PAGE_ALLOCATION_GRANULARITY (0x1000)
+
+//
+// Modifier to ensure that all protocol member functions and EFI intrinsics
+// use the correct C calling convention. All protocol member functions and
+// EFI intrinsics are required to modify their member functions with EFIAPI.
+//
+#ifdef EFIAPI
+ ///
+ /// If EFIAPI is already defined, then we use that definition.
+ ///
+#elif defined(__GNUC__)
+ ///
+ /// Define the standard calling convention regardless of optimization level
+ /// The GCC support assumes a GCC compiler that supports the EFI ABI. The EFI
+ /// ABI is much closer to the x64 Microsoft* ABI than standard x64 (x86-64)
+ /// GCC ABI. Thus a standard x64 (x86-64) GCC compiler can not be used for
+ /// x64. Warning the assembly code in the MDE x64 does not follow the correct
+ /// ABI for the standard x64 (x86-64) GCC.
+ ///
+ #define EFIAPI
+#else
+ ///
+ /// The default for a non Microsoft* or GCC compiler is to assume the EFI ABI
+ /// is the standard.
+ ///
+ #define EFIAPI
+#endif
+
+#if defined(__GNUC__)
+ ///
+ /// For GNU assembly code, .global or .globl can declare global symbols.
+ /// Define this macro to unify the usage.
+ ///
+ #define ASM_GLOBAL .globl
+#endif
+
+/**
+ Return the pointer to the first instruction of a function given a function pointer.
+ On x64 CPU architectures, these two pointer values are the same,
+ so the implementation of this macro is very simple.
+
+ @param FunctionPointer A pointer to a function.
+
+ @return The pointer to the first instruction of a function given a function pointer.
+
+**/
+#define FUNCTION_ENTRY_POINT(FunctionPointer) (VOID *)(UINTN)(FunctionPointer)
+
+#ifndef __USER_LABEL_PREFIX__
+#define __USER_LABEL_PREFIX__
+#endif
+
+#endif
diff --git a/MdePkg/MdePkg.dec b/MdePkg/MdePkg.dec index 6c37c21..0b9c4bc 100644 --- a/MdePkg/MdePkg.dec +++ b/MdePkg/MdePkg.dec @@ -6,7 +6,7 @@ #
# Copyright (c) 2007 - 2019, Intel Corporation. All rights reserved.<BR>
# Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
-# (C) Copyright 2016 Hewlett Packard Enterprise Development LP<BR>
+# (C) Copyright 2016 - 2020 Hewlett Packard Enterprise Development LP<BR>
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
@@ -39,6 +39,9 @@ [Includes.AARCH64]
Include/AArch64
+[Includes.RISCV64]
+ Include/RiscV64
+
[LibraryClasses]
## @libraryclass Provides most usb APIs to support the Hid requests defined in Usb Hid 1.1 spec
# and the standard requests defined in Usb 1.1 spec.
diff --git a/MdePkg/MdePkg.dsc b/MdePkg/MdePkg.dsc index 2b2d598..6cd38e7 100644 --- a/MdePkg/MdePkg.dsc +++ b/MdePkg/MdePkg.dsc @@ -3,6 +3,7 @@ #
# Copyright (c) 2007 - 2018, Intel Corporation. All rights reserved.<BR>
# Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
+# (C) Copyright 2020 Hewlett Packard Enterprise Development LP<BR>
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
@@ -14,7 +15,7 @@ PLATFORM_VERSION = 1.08
DSC_SPECIFICATION = 0x00010005
OUTPUT_DIRECTORY = Build/Mde
- SUPPORTED_ARCHITECTURES = IA32|X64|EBC|ARM|AARCH64
+ SUPPORTED_ARCHITECTURES = IA32|X64|EBC|ARM|AARCH64|RISCV64
BUILD_TARGETS = DEBUG|RELEASE|NOOPT
SKUID_IDENTIFIER = DEFAULT
|