diff options
| author | Dhaval Sharma <dhaval@rivosinc.com> | 2024-01-29 09:31:16 +0530 |
|---|---|---|
| committer | mergify[bot] <37929162+mergify[bot]@users.noreply.github.com> | 2024-02-04 03:09:12 +0000 |
| commit | 141dcaed6cc930d83a4f95cb51ebc22f51fcc32c (patch) | |
| tree | 8e756f291721d1a2f8c3ec49d6ea8f8f27829259 | |
| parent | cd6f2152237713d12723a55aa258c7ae91577dff (diff) | |
| download | edk2-141dcaed6cc930d83a4f95cb51ebc22f51fcc32c.zip edk2-141dcaed6cc930d83a4f95cb51ebc22f51fcc32c.tar.gz edk2-141dcaed6cc930d83a4f95cb51ebc22f51fcc32c.tar.bz2 | |
UefiCpuPkg: Add cache operations support for Arch proto
With CMO operations available for RISC-V, utilize them in CPU
Architecture protocol.
Signed-off-by: Dhaval Sharma <dhaval@rivosinc.com>
Cc: Gerd Hoffmann <kraxel@redhat.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Cc: Rahul Kumar <rahul1.kumar@intel.com>
Cc: Ray Ni <ray.ni@intel.com>
Cc: Sunil VL <sunilvl@ventanamicro.com>
Cc: Andrei Warkentin <andrei.warkentin@intel.com>
Reviewed-by: Sunil V L <sunilvl@ventanamicro.com>
| -rw-r--r-- | UefiCpuPkg/CpuDxeRiscV64/CpuDxe.c | 14 | ||||
| -rw-r--r-- | UefiCpuPkg/CpuDxeRiscV64/CpuDxe.h | 1 |
2 files changed, 15 insertions, 0 deletions
diff --git a/UefiCpuPkg/CpuDxeRiscV64/CpuDxe.c b/UefiCpuPkg/CpuDxeRiscV64/CpuDxe.c index 2af3b62..c6bae10 100644 --- a/UefiCpuPkg/CpuDxeRiscV64/CpuDxe.c +++ b/UefiCpuPkg/CpuDxeRiscV64/CpuDxe.c @@ -90,6 +90,20 @@ CpuFlushCpuDataCache ( IN EFI_CPU_FLUSH_TYPE FlushType
)
{
+ switch (FlushType) {
+ case EfiCpuFlushTypeWriteBack:
+ WriteBackDataCacheRange ((VOID *)(UINTN)Start, (UINTN)Length);
+ break;
+ case EfiCpuFlushTypeInvalidate:
+ InvalidateDataCacheRange ((VOID *)(UINTN)Start, (UINTN)Length);
+ break;
+ case EfiCpuFlushTypeWriteBackInvalidate:
+ WriteBackInvalidateDataCacheRange ((VOID *)(UINTN)Start, (UINTN)Length);
+ break;
+ default:
+ return EFI_INVALID_PARAMETER;
+ }
+
return EFI_SUCCESS;
}
diff --git a/UefiCpuPkg/CpuDxeRiscV64/CpuDxe.h b/UefiCpuPkg/CpuDxeRiscV64/CpuDxe.h index 68e6d03..d4d6777 100644 --- a/UefiCpuPkg/CpuDxeRiscV64/CpuDxe.h +++ b/UefiCpuPkg/CpuDxeRiscV64/CpuDxe.h @@ -17,6 +17,7 @@ #include <Library/BaseRiscVSbiLib.h>
#include <Library/BaseRiscVMmuLib.h>
#include <Library/BaseLib.h>
+#include <Library/CacheMaintenanceLib.h>
#include <Library/CpuExceptionHandlerLib.h>
#include <Library/DebugLib.h>
#include <Library/UefiBootServicesTableLib.h>
|