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author | Abner Chang <abner.chang@hpe.com> | 2020-04-03 13:49:35 +0800 |
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committer | mergify[bot] <37929162+mergify[bot]@users.noreply.github.com> | 2020-05-07 03:17:15 +0000 |
commit | 722da9078eb03317f23d61f33f8f1f3e1dd78396 (patch) | |
tree | 68902ff019e005e771955d4319e98d534fa0ddd0 /.pytool/Plugin | |
parent | ea56fa3d4706dae4e662e01fddb24a2826abfcbd (diff) | |
download | edk2-722da9078eb03317f23d61f33f8f1f3e1dd78396.zip edk2-722da9078eb03317f23d61f33f8f1f3e1dd78396.tar.gz edk2-722da9078eb03317f23d61f33f8f1f3e1dd78396.tar.bz2 |
.azurepipelines: Add RISC-V architecture on RISC-V EDK2 CI.
BZ:2562:
https://bugzilla.tianocore.org/show_bug.cgi?id=2562
Add RISC-V architecture on RISC-V EDK2 CI.
Signed-off-by: Abner Chang <abner.chang@hpe.com>
Reviewed-by: Sean Brogan <sean.brogan@microsoft.com>
Cc: Bret Barkelew <Bret.Barkelew@microsoft.com>
Cc: Sean Brogan <sean.brogan@microsoft.com>
Cc: Leif Lindholm <leif@nuviainc.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Gilbert Chen <gilbert.chen@hpe.com>
Cc: Daniel Helmut Schaefer <daniel.schaefer@hpe.com>
Diffstat (limited to '.pytool/Plugin')
0 files changed, 0 insertions, 0 deletions