blob: d077e40f42780aab819c0b004e9d70c7471e3718 (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
|
#!/usr/bin/env python3
#
# OpenSBI boot test for RISC-V machines
#
# Copyright (c) 2022, Ventana Micro
#
# This work is licensed under the terms of the GNU GPL, version 2 or
# later. See the COPYING file in the top-level directory.
from qemu_test import QemuSystemTest
from qemu_test import wait_for_console_pattern
class RiscvOpenSBI(QemuSystemTest):
timeout = 5
def boot_opensbi(self):
self.vm.set_console()
self.vm.launch()
wait_for_console_pattern(self, 'Platform Name')
wait_for_console_pattern(self, 'Boot HART MEDELEG')
def test_riscv_spike(self):
self.set_machine('spike')
self.boot_opensbi()
def test_riscv_sifive_u(self):
self.set_machine('sifive_u')
self.boot_opensbi()
def test_riscv_virt(self):
self.set_machine('virt')
self.boot_opensbi()
if __name__ == '__main__':
QemuSystemTest.main()
|
