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/*
* Generic vector operation descriptor
*
* Copyright (c) 2018 Linaro
*
* This library is free software; you can redistribute it and/or
* modify it under the terms of the GNU Lesser General Public
* License as published by the Free Software Foundation; either
* version 2.1 of the License, or (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public
* License along with this library; if not, see <http://www.gnu.org/licenses/>.
*/
/* ??? These bit widths are set for ARM SVE, maxing out at 256 byte vectors. */
#define SIMD_OPRSZ_SHIFT 0
#define SIMD_OPRSZ_BITS 5
#define SIMD_MAXSZ_SHIFT (SIMD_OPRSZ_SHIFT + SIMD_OPRSZ_BITS)
#define SIMD_MAXSZ_BITS 5
#define SIMD_DATA_SHIFT (SIMD_MAXSZ_SHIFT + SIMD_MAXSZ_BITS)
#define SIMD_DATA_BITS (32 - SIMD_DATA_SHIFT)
/* Create a descriptor from components. */
uint32_t simd_desc(uint32_t oprsz, uint32_t maxsz, int32_t data);
/* Extract the operation size from a descriptor. */
static inline intptr_t simd_oprsz(uint32_t desc)
{
return (extract32(desc, SIMD_OPRSZ_SHIFT, SIMD_OPRSZ_BITS) + 1) * 8;
}
/* Extract the max vector size from a descriptor. */
static inline intptr_t simd_maxsz(uint32_t desc)
{
return (extract32(desc, SIMD_MAXSZ_SHIFT, SIMD_MAXSZ_BITS) + 1) * 8;
}
/* Extract the operation-specific data from a descriptor. */
static inline int32_t simd_data(uint32_t desc)
{
return sextract32(desc, SIMD_DATA_SHIFT, SIMD_DATA_BITS);
}
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