target/riscv/XVentanaCondOps.decode


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#
# RISC-V translation routines for the XVentanaCondOps extension
#
# Copyright (c) 2022 Dr. Philipp Tomsich, philipp.tomsich@vrull.eu
#
# SPDX-License-Identifier: LGPL-2.1-or-later
#
# Reference: VTx-family custom instructions
#            Custom ISA extensions for Ventana Micro Systems RISC-V cores
#            (https://github.com/ventanamicro/ventana-custom-extensions/releases/download/v1.0.0/ventana-custom-extensions-v1.0.0.pdf)

# Fields
%rs2  20:5
%rs1  15:5
%rd    7:5

# Argument sets
&r    rd rs1 rs2  !extern

# Formats
@r         .......  ..... ..... ... ..... ....... &r                %rs2 %rs1 %rd

# *** RV64 Custom-3 Extension ***
vt_maskc   0000000  ..... ..... 110 ..... 1111011 @r
vt_maskcn  0000000  ..... ..... 111 ..... 1111011 @r