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#
# Power ISA decode for 64-bit prefixed insns (opcode space 0 and 1)
#
# Copyright (c) 2021 Instituto de Pesquisas Eldorado (eldorado.org.br)
#
# This library is free software; you can redistribute it and/or
# modify it under the terms of the GNU Lesser General Public
# License as published by the Free Software Foundation; either
# version 2.1 of the License, or (at your option) any later version.
#
# This library is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
# Lesser General Public License for more details.
#
# You should have received a copy of the GNU Lesser General Public
# License along with this library; if not, see <http://www.gnu.org/licenses/>.
#
# Format MLS:D and 8LS:D
&PLS_D rt ra si:int64_t r:bool
%pls_si 32:s18 0:16
@PLS_D ...... .. ... r:1 .. .................. \
...... rt:5 ra:5 ................ \
&PLS_D si=%pls_si
@8LS_D_TSX ...... .. . .. r:1 .. .................. \
..... rt:6 ra:5 ................ \
&PLS_D si=%pls_si
%rt_tsxp 21:1 22:4 !function=times_2
@8LS_D_TSXP ...... .. . .. r:1 .. .................. \
...... ..... ra:5 ................ \
&PLS_D si=%pls_si rt=%rt_tsxp
# Format 8RR:D
%8rr_si 32:s16 0:16
%8rr_xt 16:1 21:5
&8RR_D_IX xt ix si
@8RR_D_IX ...... .. .... .. .. ................ \
...... ..... ... ix:1 . ................ \
&8RR_D_IX si=%8rr_si xt=%8rr_xt
&8RR_D xt si:int32_t
@8RR_D ...... .. .... .. .. ................ \
...... ..... .... . ................ \
&8RR_D si=%8rr_si xt=%8rr_xt
# Format 8RR:XX4
%8rr_xx_xt 0:1 21:5
%8rr_xx_xa 2:1 16:5
%8rr_xx_xb 1:1 11:5
%8rr_xx_xc 3:1 6:5
&8RR_XX4 xt xa xb xc
@8RR_XX4 ........ ........ ........ ........ \
...... ..... ..... ..... ..... .. .... \
&8RR_XX4 xt=%8rr_xx_xt xa=%8rr_xx_xa xb=%8rr_xx_xb xc=%8rr_xx_xc
&8RR_XX4_imm xt xa xb xc imm
@8RR_XX4_imm ........ ........ ........ imm:8 \
...... ..... ..... ..... ..... .. .... \
&8RR_XX4_imm xt=%8rr_xx_xt xa=%8rr_xx_xa xb=%8rr_xx_xb xc=%8rr_xx_xc
&8RR_XX4_uim3 xt xa xb xc uim3
@8RR_XX4_uim3 ...... .. .... .. ............... uim3:3 \
...... ..... ..... ..... ..... .. .... \
&8RR_XX4_uim3 xt=%8rr_xx_xt xa=%8rr_xx_xa xb=%8rr_xx_xb xc=%8rr_xx_xc
### Fixed-Point Load Instructions
PLBZ 000001 10 0--.-- .................. \
100010 ..... ..... ................ @PLS_D
PLHZ 000001 10 0--.-- .................. \
101000 ..... ..... ................ @PLS_D
PLHA 000001 10 0--.-- .................. \
101010 ..... ..... ................ @PLS_D
PLWZ 000001 10 0--.-- .................. \
100000 ..... ..... ................ @PLS_D
PLWA 000001 00 0--.-- .................. \
101001 ..... ..... ................ @PLS_D
PLD 000001 00 0--.-- .................. \
111001 ..... ..... ................ @PLS_D
PLQ 000001 00 0--.-- .................. \
111000 ..... ..... ................ @PLS_D
### Fixed-Point Store Instructions
PSTW 000001 10 0--.-- .................. \
100100 ..... ..... ................ @PLS_D
PSTB 000001 10 0--.-- .................. \
100110 ..... ..... ................ @PLS_D
PSTH 000001 10 0--.-- .................. \
101100 ..... ..... ................ @PLS_D
PSTD 000001 00 0--.-- .................. \
111101 ..... ..... ................ @PLS_D
PSTQ 000001 00 0--.-- .................. \
111100 ..... ..... ................ @PLS_D
### Fixed-Point Arithmetic Instructions
PADDI 000001 10 0--.-- .................. \
001110 ..... ..... ................ @PLS_D
### Float-Point Load and Store Instructions
PLFS 000001 10 0--.-- .................. \
110000 ..... ..... ................ @PLS_D
PLFD 000001 10 0--.-- .................. \
110010 ..... ..... ................ @PLS_D
PSTFS 000001 10 0--.-- .................. \
110100 ..... ..... ................ @PLS_D
PSTFD 000001 10 0--.-- .................. \
110110 ..... ..... ................ @PLS_D
### Prefixed No-operation Instruction
@PNOP 000001 11 0000-- 000000000000000000 \
................................
{
[
## Invalid suffixes: Branch instruction
# bc[l][a]
INVALID ................................ \
010000-------------------------- @PNOP
# b[l][a]
INVALID ................................ \
010010-------------------------- @PNOP
# bclr[l]
INVALID ................................ \
010011---------------0000010000- @PNOP
# bcctr[l]
INVALID ................................ \
010011---------------1000010000- @PNOP
# bctar[l]
INVALID ................................ \
010011---------------1000110000- @PNOP
## Invalid suffixes: rfebb
INVALID ................................ \
010011---------------0010010010- @PNOP
## Invalid suffixes: context synchronizing other than isync
# sc
INVALID ................................ \
010001------------------------1- @PNOP
# scv
INVALID ................................ \
010001------------------------01 @PNOP
# rfscv
INVALID ................................ \
010011---------------0001010010- @PNOP
# rfid
INVALID ................................ \
010011---------------0000010010- @PNOP
# hrfid
INVALID ................................ \
010011---------------0100010010- @PNOP
# urfid
INVALID ................................ \
010011---------------0100110010- @PNOP
# stop
INVALID ................................ \
010011---------------0101110010- @PNOP
# mtmsr w/ L=0
INVALID ................................ \
011111---------0-----0010010010- @PNOP
# mtmsrd w/ L=0
INVALID ................................ \
011111---------0-----0010110010- @PNOP
## Invalid suffixes: Service Processor Attention
INVALID ................................ \
000000----------------100000000- @PNOP
]
## Valid suffixes
PNOP ................................ \
-------------------------------- @PNOP
}
### VSX instructions
PLXV 000001 00 0--.-- .................. \
11001 ...... ..... ................ @8LS_D_TSX
PSTXV 000001 00 0--.-- .................. \
11011 ...... ..... ................ @8LS_D_TSX
PLXVP 000001 00 0--.-- .................. \
111010 ..... ..... ................ @8LS_D_TSXP
PSTXVP 000001 00 0--.-- .................. \
111110 ..... ..... ................ @8LS_D_TSXP
XXEVAL 000001 01 0000 -- ---------- ........ \
100010 ..... ..... ..... ..... 01 .... @8RR_XX4_imm
XXSPLTIDP 000001 01 0000 -- -- ................ \
100000 ..... 0010 . ................ @8RR_D
XXSPLTIW 000001 01 0000 -- -- ................ \
100000 ..... 0011 . ................ @8RR_D
XXSPLTI32DX 000001 01 0000 -- -- ................ \
100000 ..... 000 .. ................ @8RR_D_IX
XXBLENDVD 000001 01 0000 -- ------------------ \
100001 ..... ..... ..... ..... 11 .... @8RR_XX4
XXBLENDVW 000001 01 0000 -- ------------------ \
100001 ..... ..... ..... ..... 10 .... @8RR_XX4
XXBLENDVH 000001 01 0000 -- ------------------ \
100001 ..... ..... ..... ..... 01 .... @8RR_XX4
XXBLENDVB 000001 01 0000 -- ------------------ \
100001 ..... ..... ..... ..... 00 .... @8RR_XX4
XXPERMX 000001 01 0000 -- --------------- ... \
100010 ..... ..... ..... ..... 00 .... @8RR_XX4_uim3
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