blob: 2c57f78fc19984c0ecd79d87b0ce1cee3fa34312 (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
|
#ifndef QEMU_CACHE_UTILS_H
#define QEMU_CACHE_UTILS_H
#if defined(_ARCH_PPC)
#include <stdint.h> /* uintptr_t */
struct qemu_cache_conf {
unsigned long dcache_bsize;
unsigned long icache_bsize;
};
extern struct qemu_cache_conf qemu_cache_conf;
void qemu_cache_utils_init(char **envp);
/* mildly adjusted code from tcg-dyngen.c */
static inline void flush_icache_range(uintptr_t start, uintptr_t stop)
{
unsigned long p, start1, stop1;
unsigned long dsize = qemu_cache_conf.dcache_bsize;
unsigned long isize = qemu_cache_conf.icache_bsize;
start1 = start & ~(dsize - 1);
stop1 = (stop + dsize - 1) & ~(dsize - 1);
for (p = start1; p < stop1; p += dsize) {
asm volatile ("dcbst 0,%0" : : "r"(p) : "memory");
}
asm volatile ("sync" : : : "memory");
start &= start & ~(isize - 1);
stop1 = (stop + isize - 1) & ~(isize - 1);
for (p = start1; p < stop1; p += isize) {
asm volatile ("icbi 0,%0" : : "r"(p) : "memory");
}
asm volatile ("sync" : : : "memory");
asm volatile ("isync" : : : "memory");
}
#else
#define qemu_cache_utils_init(envp) do { (void) (envp); } while (0)
#endif
#endif /* QEMU_CACHE_UTILS_H */
|
