blob: d77655d65911a14f517145755e054d0fe40d7258 (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
|
/*
* ASPEED Coprocessor
*
* Copyright (C) 2025 ASPEED Technology Inc.
*
* SPDX-License-Identifier: GPL-2.0-or-later
*/
#ifndef ASPEED_COPROCESSOR_H
#define ASPEED_COPROCESSOR_H
#include "qom/object.h"
#include "hw/arm/aspeed_soc.h"
struct AspeedCoprocessorState {
DeviceState parent;
MemoryRegion *memory;
MemoryRegion sram;
Clock *sysclk;
AspeedSCUState scu;
AspeedSCUState scuio;
AspeedTimerCtrlState timerctrl;
SerialMM uart[ASPEED_UARTS_NUM];
};
#define TYPE_ASPEED_COPROCESSOR "aspeed-coprocessor"
OBJECT_DECLARE_TYPE(AspeedCoprocessorState, AspeedCoprocessorClass,
ASPEED_COPROCESSOR)
struct AspeedCoprocessorClass {
DeviceClass parent_class;
/** valid_cpu_types: NULL terminated array of a single CPU type. */
const char * const *valid_cpu_types;
uint32_t silicon_rev;
const hwaddr *memmap;
const int *irqmap;
int uarts_base;
int uarts_num;
};
struct Aspeed27x0CoprocessorState {
AspeedCoprocessorState parent;
AspeedINTCState intc[2];
UnimplementedDeviceState ipc[2];
UnimplementedDeviceState scuio;
ARMv7MState armv7m;
};
#define TYPE_ASPEED27X0SSP_COPROCESSOR "aspeed27x0ssp-coprocessor"
OBJECT_DECLARE_SIMPLE_TYPE(Aspeed27x0CoprocessorState,
ASPEED27X0SSP_COPROCESSOR)
#define TYPE_ASPEED27X0TSP_COPROCESSOR "aspeed27x0tsp-coprocessor"
DECLARE_OBJ_CHECKERS(Aspeed27x0CoprocessorState, AspeedCoprocessorClass,
ASPEED27X0TSP_COPROCESSOR, TYPE_ASPEED27X0TSP_COPROCESSOR)
#endif /* ASPEED_COPROCESSOR_H */
|
