blob: 8acb9c746697f96b5c87ccf3baebbfc88ec7c3ed (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
|
/*
* QEMU ATI SVGA emulation
*
* Copyright (c) 2019 BALATON Zoltan
*
* This work is licensed under the GNU GPL license version 2 or later.
*/
#ifndef ATI_INT_H
#define ATI_INT_H
#include "qemu/timer.h"
#include "hw/pci/pci.h"
#include "hw/i2c/bitbang_i2c.h"
#include "vga_int.h"
#include "qom/object.h"
/*#define DEBUG_ATI*/
#ifdef DEBUG_ATI
#define DPRINTF(fmt, ...) printf("%s: " fmt, __func__, ## __VA_ARGS__)
#else
#define DPRINTF(fmt, ...) do {} while (0)
#endif
#define PCI_VENDOR_ID_ATI 0x1002
/* Rage128 Pro GL */
#define PCI_DEVICE_ID_ATI_RAGE128_PF 0x5046
/* Radeon RV100 (VE) */
#define PCI_DEVICE_ID_ATI_RADEON_QY 0x5159
#define TYPE_ATI_VGA "ati-vga"
OBJECT_DECLARE_SIMPLE_TYPE(ATIVGAState, ATI_VGA)
typedef struct ATIVGARegs {
uint32_t mm_index;
uint32_t bios_scratch[8];
uint32_t gen_int_cntl;
uint32_t gen_int_status;
uint32_t crtc_gen_cntl;
uint32_t crtc_ext_cntl;
uint32_t dac_cntl;
uint32_t gpio_vga_ddc;
uint32_t gpio_dvi_ddc;
uint32_t gpio_monid;
uint32_t config_cntl;
uint32_t crtc_h_total_disp;
uint32_t crtc_h_sync_strt_wid;
uint32_t crtc_v_total_disp;
uint32_t crtc_v_sync_strt_wid;
uint32_t crtc_offset;
uint32_t crtc_offset_cntl;
uint32_t crtc_pitch;
uint32_t cur_offset;
uint32_t cur_hv_pos;
uint32_t cur_hv_offs;
uint32_t cur_color0;
uint32_t cur_color1;
uint32_t dst_offset;
uint32_t dst_pitch;
uint32_t dst_tile;
uint32_t dst_width;
uint32_t dst_height;
uint32_t src_offset;
uint32_t src_pitch;
uint32_t src_tile;
uint32_t src_x;
uint32_t src_y;
uint32_t dst_x;
uint32_t dst_y;
uint32_t dp_gui_master_cntl;
uint32_t dp_brush_bkgd_clr;
uint32_t dp_brush_frgd_clr;
uint32_t dp_src_frgd_clr;
uint32_t dp_src_bkgd_clr;
uint32_t dp_cntl;
uint32_t dp_datatype;
uint32_t dp_mix;
uint32_t dp_write_mask;
uint32_t default_offset;
uint32_t default_pitch;
uint32_t default_tile;
uint32_t default_sc_bottom_right;
} ATIVGARegs;
struct ATIVGAState {
PCIDevice dev;
VGACommonState vga;
char *model;
uint16_t dev_id;
uint8_t mode;
bool cursor_guest_mode;
uint16_t cursor_size;
uint32_t cursor_offset;
QEMUCursor *cursor;
QEMUTimer vblank_timer;
bitbang_i2c_interface bbi2c;
MemoryRegion io;
MemoryRegion mm;
ATIVGARegs regs;
};
const char *ati_reg_name(int num);
void ati_2d_blt(ATIVGAState *s);
#endif /* ATI_INT_H */
|
