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2023-03-01tests/docker: Use binaries for debian-tricore-crossBastian Koppelmann2-4/+4
since binutils is pretty old, it fails our CI repeatedly during the compilation of tricore-binutils. We created a precompiled version using the debian docker image and download it instead of building it ourself. We also updated the package to include a newer version of binutils, gcc, and newlib. The default TriCore ISA version used by tricore-as changed from the old version, so we have to specify it now. If we don't 'test_fadd' fails with 'unknown opcode'. The new assembler also picks a new encoding in ld.h which fails the 'test_ld_h' test. We fix that by using the newest TriCore CPU for QEMU. The old assembler accepted an extra ')' in 'test_imask'. The new one does not, so lets remove it. Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Message-Id: <20230209145812.46730-1-kbastian@mail.uni-paderborn.de> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20230228190653.1602033-12-alex.bennee@linaro.org>
2023-02-27Merge tag 'for-upstream-8.0' of https://gitlab.com/bonzini/qemu into stagingPeter Maydell1-0/+3
* New Sapphire Rapids model support * x86 bugfixes * Prepare to drop support for Python 3.6 # -----BEGIN PGP SIGNATURE----- # # iQFIBAABCAAyFiEE8TM4V0tmI4mGbHaCv/vSX3jHroMFAmP87gcUHHBib256aW5p # QHJlZGhhdC5jb20ACgkQv/vSX3jHroM+TAf/TcRrukw+FXUs0Ld3AadRY6g3xV2x # n1VIfkMC2Bp1LVOS1W9aw7V6jPg8KMAV9SCQJjsVtyB5E9yPQg+/w7UgexqISYQG # 7NK3jDXmslSGIHNHh4qH9xAjQGjw/6e7N/gyWP+99vHPwZSbFJT6k7KP0/3O9yCu # /9KINq8AvvGbfW5m2d/umV1v1Gq4KwXkTa5uVIOciDMJtaA0QjADHg1MqsHPzBUP # F4du5BbuMaJkgQgJV5zsn7W9NnEQt1XzSug1c/vp2vyqEV00L4TjL9BzTqsTEBtS # KjUcQif5R5a+o8QRND9j8f74xjFpOR/nAEleNsfo6iwZQwWAiBQZ8ETsew== # =2aMG # -----END PGP SIGNATURE----- # gpg: Signature made Mon 27 Feb 2023 17:53:11 GMT # gpg: using RSA key F13338574B662389866C7682BFFBD25F78C7AE83 # gpg: issuer "pbonzini@redhat.com" # gpg: Good signature from "Paolo Bonzini <bonzini@gnu.org>" [full] # gpg: aka "Paolo Bonzini <pbonzini@redhat.com>" [full] # Primary key fingerprint: 46F5 9FBD 57D6 12E7 BFD4 E2F7 7E15 100C CD36 69B1 # Subkey fingerprint: F133 3857 4B66 2389 866C 7682 BFFB D25F 78C7 AE83 * tag 'for-upstream-8.0' of https://gitlab.com/bonzini/qemu: i386: Add new CPU model SapphireRapids target/i386: KVM: allow fast string operations if host supports them target/i386: add FZRM, FSRS, FSRC target/i386: add FSRM to TCG MAINTAINERS: Cover RCU documentation ci, docker: update CentOS and OpenSUSE Python to non-EOL versions docs/devel: update and clarify lcitool instructions lcitool: update submodule configure: Look for auxiliary Python installations configure: protect against escaping venv when running Meson meson: stop looking for 'sphinx-build-3' meson: Avoid duplicates in generated config-poison.h again target/i386: Fix BZHI instruction Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2023-02-27target/i386: Fix BZHI instructionRichard Henderson1-0/+3
We did not correctly handle N >= operand size. Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1374 Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20230114233206.3118472-1-richard.henderson@linaro.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2023-02-27tests/tcg/s390x: Add sam.SIlya Leoshkevich2-0/+68
Add a small test to prevent regressions. Signed-off-by: Ilya Leoshkevich <iii@linux.ibm.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20221129015328.55439-1-iii@linux.ibm.com> Message-Id: <20230220184052.163465-7-richard.henderson@linaro.org> Signed-off-by: Thomas Huth <thuth@redhat.com>
2023-02-27tests/tcg/s390x: Add bal.SIlya Leoshkevich2-0/+25
Add a small test to prevent regressions. Signed-off-by: Ilya Leoshkevich <iii@linux.ibm.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20221103130011.2670186-1-iii@linux.ibm.com> Message-Id: <20230220184052.163465-6-richard.henderson@linaro.org> Signed-off-by: Thomas Huth <thuth@redhat.com>
2023-02-16target/i386: Fix 32-bit AD[CO]X insns in 64-bit modeRichard Henderson2-0/+72
Failure to truncate the inputs results in garbage for the carry-out. Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1373 Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <20230115012103.3131796-1-richard.henderson@linaro.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2023-02-16Merge tag 'for-upstream' of https://gitlab.com/bonzini/qemu into stagingPeter Maydell3-90/+185
* block/iscsi: fix double-free on BUSY or similar statuses * catch [accel] entry without accelerator * target/i386: various fixes for BMI and ADX instructions * make the contents of meson-buildoptions.sh stable # -----BEGIN PGP SIGNATURE----- # # iQFIBAABCAAyFiEE8TM4V0tmI4mGbHaCv/vSX3jHroMFAmPpDTcUHHBib256aW5p # QHJlZGhhdC5jb20ACgkQv/vSX3jHroODWAgAhWi0XSBe91+34ahQqx6JoLStNX9e # xy1Cm/5LPDrDquD/4T6gnzb1Min/X2AsVu9c+VIbuHbL/rFc7aNIEL6c7KzwSFLs # vEDF7tSnlIMK0ClDsDYBz7HUIgBgqE2crAJmTJus2Cqd+Ef5bMxhQi5Imrk6qtmO # HRdVYEGasJ7CO50oUB91AMrNInWQw0qBnBOB8TnwTLTcvE1txa+xnZuZgQA2HrGX # OweLdKRcYPvRYvBB3wLMbwqEKbD1eYbdbNt7T2KkuVQpYcgfoCpayHIIMroD+hvu # BImmG9wWieDKH4Brs765gH6/3VF5UZKbgDQo9Wz+W/5QqnqRSsOYBiMkmA== # =G3PN # -----END PGP SIGNATURE----- # gpg: Signature made Sun 12 Feb 2023 16:00:55 GMT # gpg: using RSA key F13338574B662389866C7682BFFBD25F78C7AE83 # gpg: issuer "pbonzini@redhat.com" # gpg: Good signature from "Paolo Bonzini <bonzini@gnu.org>" [full] # gpg: aka "Paolo Bonzini <pbonzini@redhat.com>" [full] # Primary key fingerprint: 46F5 9FBD 57D6 12E7 BFD4 E2F7 7E15 100C CD36 69B1 # Subkey fingerprint: F133 3857 4B66 2389 866C 7682 BFFB D25F 78C7 AE83 * tag 'for-upstream' of https://gitlab.com/bonzini/qemu: libqtest: ensure waitpid() is only called once libqtest: split qtest_spawn_qemu function target/i386: fix ADOX followed by ADCX target/i386: Fix C flag for BLSI, BLSMSK, BLSR target/i386: Fix BEXTR instruction tests/tcg/i386: Introduce and use reg_t consistently vl: catch [accel] entry without accelerator block/iscsi: fix double-free on BUSY or similar statuses remove unnecessary extern "C" blocks build: make meson-buildoptions.sh stable Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2023-02-14tests/tcg/s390x: Use -nostdlib for softmmu testsIlya Leoshkevich1-1/+1
The code currently uses -nostartfiles, but this does not prevent linking with libc. On Fedora there is no cross-libc, so the linking step fails. Fix by using the more comprehensive -nostdlib (that's also what probe_target_compiler() checks for as well). Fixes: 503e549e441e ("tests/tcg/s390x: Test unaligned accesses to lowcore") Signed-off-by: Ilya Leoshkevich <iii@linux.ibm.com> Message-Id: <20230131182057.2261614-1-iii@linux.ibm.com> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Thomas Huth <thuth@redhat.com>
2023-02-11target/i386: fix ADOX followed by ADCXPaolo Bonzini2-1/+80
When ADCX is followed by ADOX or vice versa, the second instruction's carry comes from EFLAGS and the condition codes use the CC_OP_ADCOX operation. Retrieving the carry from EFLAGS is handled by this bit of gen_ADCOX: tcg_gen_extract_tl(carry_in, cpu_cc_src, ctz32(cc_op == CC_OP_ADCX ? CC_C : CC_O), 1); Unfortunately, in this case cc_op has been overwritten by the previous "if" statement to CC_OP_ADCOX. This works by chance when the first instruction is ADCX; however, if the first instruction is ADOX, ADCX will incorrectly take its carry from OF instead of CF. Fix by moving the computation of the new cc_op at the end of the function. The included exhaustive test case fails without this patch and passes afterwards. Because ADCX/ADOX need not be invoked through the VEX prefix, this regression bisects to commit 16fc5726a6e2 ("target/i386: reimplement 0x0f 0x38, add AVX", 2022-10-18). However, the mistake happened a little earlier, when BMI instructions were rewritten using the new decoder framework. Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1471 Reported-by: Paul Jolly <https://gitlab.com/myitcv> Fixes: 1d0b926150e5 ("target/i386: move scalar 0F 38 and 0F 3A instruction to new decoder", 2022-10-18) Cc: qemu-stable@nongnu.org Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2023-02-11target/i386: Fix BEXTR instructionRichard Henderson1-0/+12
There were two problems here: not limiting the input to operand bits, and not correctly handling large extraction length. Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1372 Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20230114230542.3116013-3-richard.henderson@linaro.org> Cc: qemu-stable@nongnu.org Fixes: 1d0b926150e5 ("target/i386: move scalar 0F 38 and 0F 3A instruction to new decoder", 2022-10-18) Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2023-02-11tests/tcg/i386: Introduce and use reg_t consistentlyRichard Henderson1-89/+93
Define reg_t based on the actual register width. Define the inlines using that type. This will allow input registers to 32-bit insns to be set to 64-bit values on x86-64, which allows testing various edge cases. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <20230114230542.3116013-2-richard.henderson@linaro.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2023-02-08tests/tcg/tricore: Add test for ld.hBastian Koppelmann3-0/+29
this exercises the error reported in https://gitlab.com/qemu-project/qemu/-/issues/652. Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Message-Id: <20230203132132.511254-1-kbastian@mail.uni-paderborn.de> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
2023-02-08tests/tcg/tricore: Add LD.BU testsBastian Koppelmann3-0/+39
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Message-Id: <20230202120432.1268-11-kbastian@mail.uni-paderborn.de> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
2023-02-08tests/tcg/tricore: Add OPC2_32_RRRR_DEXTR testsBastian Koppelmann2-0/+44
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Message-Id: <20230202120432.1268-9-kbastian@mail.uni-paderborn.de> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
2023-02-08tests/tcg/tricore: Add tests for RRPW_DEXTRBastian Koppelmann3-0/+49
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Message-Id: <20230202120432.1268-7-kbastian@mail.uni-paderborn.de> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
2023-02-08tests/tcg/tricore: Add test for OPC2_32_RCRW_INSERTBastian Koppelmann3-4/+22
DREG_RS2 and DREG_CALC_RESULT were mapped to the same register which would not trigger https://gitlab.com/qemu-project/qemu/-/issues/653. So let's make each register unique. Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Message-Id: <20230202120432.1268-5-kbastian@mail.uni-paderborn.de> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
2023-02-08tests/tcg/tricore: Add test for OPC2_32_RCRW_IMASKBastian Koppelmann3-0/+18
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Message-Id: <20230202120432.1268-3-kbastian@mail.uni-paderborn.de> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
2023-02-04target/s390x: Use a single return for helper_divs64/u64Richard Henderson1-0/+35
Pack the quotient and remainder into a single Int128. Use the divu128 primitive to remove the cpu_abort on 32-bit hosts. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Acked-by: Ilya Leoshkevich <iii@linux.ibm.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> --- v2: Extended div test case to cover these insns.
2023-02-04tests/tcg/s390x: Add cdsg.cIlya Leoshkevich2-0/+97
Add a simple test to prevent regressions. Signed-off-by: Ilya Leoshkevich <iii@linux.ibm.com> Message-Id: <20230201133257.3223115-1-iii@linux.ibm.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-02-04tests/tcg/s390x: Add long-double.cRichard Henderson2-0/+25
Acked-by: Ilya Leoshkevich <iii@linux.ibm.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-02-04tests/tcg/s390x: Add clst.cIlya Leoshkevich2-0/+83
Add a basic test to prevent regressions. Signed-off-by: Ilya Leoshkevich <iii@linux.ibm.com> Message-Id: <20221025213008.2209006-2-iii@linux.ibm.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-02-04tests/tcg/s390x: Add div.cIlya Leoshkevich2-0/+41
Add a basic test to prevent regressions. Signed-off-by: Ilya Leoshkevich <iii@linux.ibm.com> Message-Id: <20221101111300.2539919-1-iii@linux.ibm.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-02-02tests/tcg: add memory-sve test for aarch64Alex Bennée2-1/+9
This will be helpful in debugging problems with tracking SVE memory accesses via the TCG plugins system. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Cc: Robert Henry <robhenry@microsoft.com> Cc: Aaron Lindsay <aaron@os.amperecomputing.com> Message-Id: <20230124180127.1881110-26-alex.bennee@linaro.org>
2023-02-02tests/tcg: Use SIGKILL for timeoutRichard Henderson1-2/+2
linux-user blocks all signals while attempting to handle guest signals (e.g. ABRT), which means that the default TERM sent by timeout has no effect -- KILL instead. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20230117035701.168514-2-richard.henderson@linaro.org> [AJB: expanded commit message from cover letter] Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <20230124180127.1881110-17-alex.bennee@linaro.org>
2023-02-02tests/tcg: skip the vma-pthread test on CIAlex Bennée1-0/+9
We are getting a lot of failures that are not related to changes so this could be a flaky test. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20230124180127.1881110-16-alex.bennee@linaro.org>
2023-01-06Merge tag 'pull-riscv-to-apply-20230106' of ↵Peter Maydell3-0/+40
https://github.com/alistair23/qemu into staging First RISC-V PR for QEMU 8.0 * Fix PMP propagation for tlb * Collection of bug fixes * Bump the OpenTitan supported version * Add smstateen support * Support native debug icount trigger * Remove the redundant ipi-id property in the virt machine * Support cache-related PMU events in virtual mode * Add some missing PolarFire SoC io regions * Fix mret exception cause when no pmp rule is configured * Fix bug where disabling compressed instructions would crash QEMU * Add Zawrs ISA extension support * A range of code refactoring and cleanups # gpg: Signature made Fri 06 Jan 2023 00:47:23 GMT # gpg: using RSA key F6C4AC46D4934868D3B8CE8F21E10D29DF977054 # gpg: Good signature from "Alistair Francis <alistair@alistair23.me>" [full] # Primary key fingerprint: F6C4 AC46 D493 4868 D3B8 CE8F 21E1 0D29 DF97 7054 * tag 'pull-riscv-to-apply-20230106' of https://github.com/alistair23/qemu: (43 commits) hw/intc: sifive_plic: Fix the pending register range check hw/riscv: opentitan: Drop "hartid-base" and "priority-base" initialization hw/intc: sifive_plic: Change "priority-base" to start from interrupt source 0 hw/riscv: virt: Fix the value of "riscv, ndev" in the dtb hw/riscv: sifive_u: Avoid using magic number for "riscv, ndev" hw/riscv: sifive_e: Fix the number of interrupt sources of PLIC hw/riscv: microchip_pfsoc: Fix the number of interrupt sources of PLIC hw/intc: sifive_plic: Update "num-sources" property default value hw/intc: sifive_plic: Use error_setg() to propagate the error up via errp in sifive_plic_realize() hw/intc: sifive_plic: Improve robustness of the PLIC config parser hw/intc: sifive_plic: Drop PLICMode_H hw/riscv: spike: Remove misleading comments hw/riscv: Sort machines Kconfig options in alphabetical order hw/riscv: Fix opentitan dependency to SIFIVE_PLIC hw/intc: Select MSI_NONBROKEN in RISC-V AIA interrupt controllers hw/riscv: Select MSI_NONBROKEN in SIFIVE_PLIC RISC-V: Add Zawrs ISA extension support target/riscv: Clear mstatus.MPRV when leaving M-mode for priv spec 1.12+ target/riscv: Simplify helper_sret() a little bit target/riscv: Set pc_succ_insn for !rvc illegal insn ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2023-01-06Merge tag 'pull-tcg-20230105' of https://gitlab.com/rth7680/qemu into stagingPeter Maydell4-15/+236
Fix race conditions in new user-only vma tracking. Add tcg backend paired register allocation. Cleanup tcg backend function call abi. # gpg: Signature made Fri 06 Jan 2023 03:12:17 GMT # gpg: using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E215F # gpg: issuer "richard.henderson@linaro.org" # gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>" [full] # Primary key fingerprint: 7A48 1E78 868B 4DB6 A85A 05C0 64DF 38E8 AF7E 215F * tag 'pull-tcg-20230105' of https://gitlab.com/rth7680/qemu: (47 commits) tests/tcg/multiarch: add vma-pthread.c accel/tcg: Handle false negative lookup in page_check_range accel/tcg: Use g_free_rcu for user-exec interval trees accel/tcg: Fix tb_invalidate_phys_page_unwind tcg: Add TCGHelperInfo argument to tcg_out_call tcg/aarch64: Merge tcg_out_callr into tcg_out_call tcg: Move ffi_cif pointer into TCGHelperInfo tcg: Factor init_ffi_layouts() out of tcg_context_init() tcg: Convert typecode_to_ffi from array to function tcg: Reorg function calls tcg: Use output_pref wrapper function tcg: Vary the allocation size for TCGOp tcg: Pass number of arguments to tcg_emit_op() / tcg_op_insert_*() accel/tcg/plugin: Use copy_op in append_{udata,mem}_cb accel/tcg/plugin: Avoid duplicate copy in copy_call accel/tcg/plugin: Don't search for the function pointer index tcg: Use TCG_CALL_ARG_EVEN for TCI special case tcg: Replace TCG_TARGET_EXTEND_ARGS with TCG_TARGET_CALL_ARG_I32 tcg: Replace TCG_TARGET_CALL_ALIGN_ARGS with TCG_TARGET_CALL_ARG_I64 tcg: Introduce TCGCallReturnKind and TCGCallArgumentKind ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2023-01-06Merge tag 'pull-hex-20230105' of https://github.com/quic/qemu into stagingPeter Maydell5-4/+242
Hexagon update: patches from several folks # gpg: Signature made Thu 05 Jan 2023 17:35:27 GMT # gpg: using RSA key 3635C788CE62B91FD4C59AB47B0244FB12DE4422 # gpg: Good signature from "Taylor Simpson (Rock on) <tsimpson@quicinc.com>" [unknown] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 3635 C788 CE62 B91F D4C5 9AB4 7B02 44FB 12DE 4422 * tag 'pull-hex-20230105' of https://github.com/quic/qemu: Update scripts/meson-buildoptions.sh Hexagon (target/hexagon) implement mutability mask for GPRs target/hexagon: suppress unused variable warning target/hexagon/idef-parser: fix two typos in README tests/tcg/hexagon: fix underspecifed asm constraints target/hexagon: rename aliased register HEX_REG_P3_0 linux-user/hexagon: fix signal context save & restore Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2023-01-06target/riscv: Set pc_succ_insn for !rvc illegal insnRichard Henderson3-0/+40
Failure to set pc_succ_insn may result in a TB covering zero bytes, which triggers an assert within the code generator. Cc: qemu-stable@nongnu.org Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1224 Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <20221203175744.151365-1-richard.henderson@linaro.org> [ Changes by AF: - Add missing run-plugin-test-noc-% line ] Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2023-01-05tests/tcg/multiarch: add vma-pthread.cIlya Leoshkevich4-15/+236
Add a test that locklessly changes and exercises page protection bits from various threads. This helps catch race conditions in the VMA handling. Acked-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Ilya Leoshkevich <iii@linux.ibm.com> Message-Id: <20221223120252.513319-1-iii@linux.ibm.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-01-05Hexagon (target/hexagon) implement mutability mask for GPRsMarco Liebel2-0/+153
Some registers are defined to have immutable bits, this commit will implement that behavior. Signed-off-by: Marco Liebel <quic_mliebel@quicinc.com> Reviewed-by: Taylor Simpson <tsimpson@quicinc.com> Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> Message-Id: <20230105102349.2181856-1-quic_mliebel@quicinc.com>
2023-01-05tests/tcg/hexagon: fix underspecifed asm constraintsMukilan Thiyagarajan2-4/+4
There are two test cases where the inline asm doesn't have the correct constraints causing them to fail. In misc.c, the 'result' output needs the early clobber modifier since the rest of the inputs are read after assignment to the output register. In mem_noshuf.c, the register r7 is written to but not specified in the clobber list. Signed-off-by: Mukilan Thiyagarajan <quic_mthiyaga@quicinc.com> Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> Reviewed-by: Taylor Simpson <tsimpson@quicinc.com> Message-Id: <20221229081836.12130-1-quic_mthiyaga@quicinc.com>
2023-01-05linux-user/hexagon: fix signal context save & restoreMukilan Thiyagarajan2-0/+85
This patch fixes the issue originally reported in this thread: https://lists.gnu.org/archive/html/qemu-devel/2021-11/msg01102.html The root cause of the issue is a bug in the hexagon specific logic for saving & restoring context during signal delivery. The CPU state has two different representations for the predicate registers. The current logic saves & restores only the aliased HEX_REG_P3_O register, which is part of env->gpr[] field in the CPU state, but not the individual byte-level predicate registers (pO, p1, p2, p3) backed by env->pred[]. Since all predicated instructions refer only to the indiviual registers, switching to and back from a signal handler can clobber these registers if the signal handler writes to them causing the normal application code to behave unpredictably when context is restored. In the reported issue with the 'signals' test, since the updated hexagon toolchain had built musl with -O2, the functions called from non_trivial_free were inlined. This meant that the code emitted reused predicate P0 computed in the entry translation block of the function non_trivial_free in one of the child TB as part of an assertion. Since P0 is clobbered by the signal handler in the signals test, the assertion in non_trivial_free fails incorectly. Since musl for hexagon implements the 'abort' function by deliberately writing to memory via null pointer, this causes the test to fail with segmentation fault. This patch modifies the signal context save & restore logic to include the individual p0, p1, p2, p3 and excludes the 32b p3_0 register since its value is derived from the former registers. It also adds a new test case that reliabily reproduces the issue for all four predicate registers. Buglink: https://github.com/quic/toolchain_for_hexagon/issues/6 Signed-off-by: Mukilan Thiyagarajan <quic_mthiyaga@quicinc.com> Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> Reviewed-by: Taylor Simpson <tsimpson@quicinc.com> Message-Id: <20221229092006.10709-2-quic_mthiyaga@quicinc.com>
2023-01-05target/arm: align exposed ID registers with LinuxZhuojia Shen2-7/+24
In CPUID registers exposed to userspace, some registers were missing and some fields were not exposed. This patch aligns exposed ID registers and their fields with what the upstream kernel currently exposes. Specifically, the following new ID registers/fields are exposed to userspace: ID_AA64PFR1_EL1.BT: bits 3-0 ID_AA64PFR1_EL1.MTE: bits 11-8 ID_AA64PFR1_EL1.SME: bits 27-24 ID_AA64ZFR0_EL1.SVEver: bits 3-0 ID_AA64ZFR0_EL1.AES: bits 7-4 ID_AA64ZFR0_EL1.BitPerm: bits 19-16 ID_AA64ZFR0_EL1.BF16: bits 23-20 ID_AA64ZFR0_EL1.SHA3: bits 35-32 ID_AA64ZFR0_EL1.SM4: bits 43-40 ID_AA64ZFR0_EL1.I8MM: bits 47-44 ID_AA64ZFR0_EL1.F32MM: bits 55-52 ID_AA64ZFR0_EL1.F64MM: bits 59-56 ID_AA64SMFR0_EL1.F32F32: bit 32 ID_AA64SMFR0_EL1.B16F32: bit 34 ID_AA64SMFR0_EL1.F16F32: bit 35 ID_AA64SMFR0_EL1.I8I32: bits 39-36 ID_AA64SMFR0_EL1.F64F64: bit 48 ID_AA64SMFR0_EL1.I16I64: bits 55-52 ID_AA64SMFR0_EL1.FA64: bit 63 ID_AA64MMFR0_EL1.ECV: bits 63-60 ID_AA64MMFR1_EL1.AFP: bits 47-44 ID_AA64MMFR2_EL1.AT: bits 35-32 ID_AA64ISAR0_EL1.RNDR: bits 63-60 ID_AA64ISAR1_EL1.FRINTTS: bits 35-32 ID_AA64ISAR1_EL1.BF16: bits 47-44 ID_AA64ISAR1_EL1.DGH: bits 51-48 ID_AA64ISAR1_EL1.I8MM: bits 55-52 ID_AA64ISAR2_EL1.WFxT: bits 3-0 ID_AA64ISAR2_EL1.RPRES: bits 7-4 ID_AA64ISAR2_EL1.GPA3: bits 11-8 ID_AA64ISAR2_EL1.APA3: bits 15-12 The code is also refactored to use symbolic names for ID register fields for better readability and maintainability. The test case in tests/tcg/aarch64/sysregs.c is also updated to match the intended behavior. Signed-off-by: Zhuojia Shen <chaosdefinition@hotmail.com> Message-id: DS7PR12MB6309FB585E10772928F14271ACE79@DS7PR12MB6309.namprd12.prod.outlook.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> [PMM: use Sn_n_Cn_Cn_n syntax to work with older assemblers that don't recognize id_aa64isar2_el1 and id_aa64mmfr2_el1] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-12-23tests/tcg: fix unused variable in linux-testAlex Bennée1-1/+5
The latest hexagon compiler picks up that we never consume wcount. Given the name of the #define that rcount checks against is WCOUNT_MAX I figured the check just got missed. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <20221221090411.1995037-5-alex.bennee@linaro.org>
2022-12-20accel/tcg: Use interval tree for user-only page trackingRichard Henderson1-0/+22
Finish weaning user-only away from PageDesc. Using an interval tree to track page permissions means that we can represent very large regions efficiently. Resolves: https://gitlab.com/qemu-project/qemu/-/issues/290 Resolves: https://gitlab.com/qemu-project/qemu/-/issues/967 Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1214 Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2022-12-16target/hexagon: import additional testsNiccolò Izzo27-1/+766
Signed-off-by: Alessandro Di Federico <ale@rev.ng> Signed-off-by: Niccolò Izzo <nizzo@rev.ng> Signed-off-by: Anton Johansson <anjo@rev.ng> Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> Reviewed-by: Taylor Simpson <tsimpson@quicinc.com> Message-Id: <20220923173831.227551-12-anjo@rev.ng>
2022-12-16Hexagon (target/hexagon) Add overrides for S2_asr_r_r_sat/S2_asl_r_r_satTaylor Simpson1-6/+28
These instructions will not be generated by idef-parser, so we override them manually. Test cases added to tests/tcg/hexagon/usr.c Co-authored-by: Matheus Tavares Bernardino <quic_mathbern@quicinc.com> Signed-off-by: Matheus Tavares Bernardino <quic_mathbern@quicinc.com> Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20221108162906.3166-4-tsimpson@quicinc.com>
2022-12-16Hexagon (target/hexagon) Fix predicated assignment to .tmp and .curTaylor Simpson1-0/+72
Here are example instructions with a predicated .tmp/.cur assignment if (p1) v12.tmp = vmem(r7 + #0) if (p0) v12.cur = vmem(r9 + #0) The .tmp/.cur indicates that references to v12 in the same packet take the result of the load. However, when the predicate is false, the value at the start of the packet should be used. After the packet commits, the .tmp value is dropped, but the .cur value is maintained. To fix this bug, we preload the original value from the HVX register into the temporary used for the result. Test cases added to tests/tcg/hexagon/hvx_misc.c Acked-by: Richard Henderson <richard.henderson@linaro.org> Co-authored-by: Matheus Tavares Bernardino <quic_mathbern@quicinc.com> Signed-off-by: Matheus Tavares Bernardino <quic_mathbern@quicinc.com> Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> Message-Id: <20221108162906.3166-3-tsimpson@quicinc.com>
2022-12-14cleanup: Tweak and re-run return_directly.cocciMarkus Armbruster1-7/+2
Tweak the semantic patch to drop redundant parenthesis around the return expression. Coccinelle drops a comment in hw/rdma/vmw/pvrdma_cmd.c; restored manually. Coccinelle messes up vmdk_co_create(), not sure why. Change dropped, will be done manually in the next commit. Line breaks in target/avr/cpu.h and hw/rdma/vmw/pvrdma_cmd.c tidied up manually. Whitespace in tools/virtiofsd/fuse_lowlevel.c tidied up manually. checkpatch.pl complains "return of an errno should typically be -ve" two times for hw/9pfs/9p-synth.c. Preexisting, the patch merely makes it visible to checkpatch.pl. Signed-off-by: Markus Armbruster <armbru@redhat.com> Message-Id: <20221122134917.1217307-2-armbru@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Acked-by: Dr. David Alan Gilbert <dgilbert@redhat.com>
2022-12-14Drop more useless casts from void * to pointerMarkus Armbruster1-2/+2
Signed-off-by: Markus Armbruster <armbru@redhat.com> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Message-Id: <20221123133811.1398562-1-armbru@redhat.com>
2022-11-15target/i386: fix cmpxchg with 32-bit register destinationPaolo Bonzini2-0/+43
Unlike the memory case, where "the destination operand receives a write cycle without regard to the result of the comparison", rm must not be touched altogether if the write fails, including not zero-extending it on 64-bit processors. This is not how the movcond currently works, because it is always followed by a gen_op_mov_reg_v to rm. To fix it, introduce a new function that is similar to gen_op_mov_reg_v but writes to a TCG temporary. Considering that gen_extu(ot, oldv) is not needed in the memory case either, the two cases for register and memory destinations are different enough that one might as well fuse the two "if (mod == 3)" into one. So do that too. Resolves: https://gitlab.com/qemu-project/qemu/-/issues/508 Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> [rth: Add a test case ] Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2022-11-01Merge tag 'pull-testing-for-7.2-011122-3' of https://github.com/stsquad/qemu ↵Stefan Hajnoczi3-19/+10
into staging testing and plugin updates for 7.2: - cleanup win32/64 docker files - update test-mingw test - add flex/bison to debian-all-test - handle --enable-static/--disable-pie in config - extend timeouts on x86_64 avocado tests - add flex/bison to debian-hexagon-cross - use regular semihosting for nios2 check-tcg - fix obscure linker error to nios2 softmmu tests - various windows portability fixes for tests - clean-up of MAINTAINERS - use -machine none when appropriate in avocado - make raspi2_initrd test detect shutdown - disable sh4 rd2 tests on gitlab - re-enable threadcount/linux-test for sh4 - clean-up s390x handling of "ex" instruction - better handle new CPUs in execlog plugin - pass CONFIG_DEBUG_TCG to plugin builds - try and avoid races in test-io-channel-command - speed up ssh key checking for tests/vm # -----BEGIN PGP SIGNATURE----- # # iQEzBAABCgAdFiEEZoWumedRZ7yvyN81+9DbCVqeKkQFAmNhI/MACgkQ+9DbCVqe # KkSFXggAg0HIpBDcNz0V5Mh5p69F14pwbDSygKqGDFBebdOHeL7f+WCvQPUGEWxp # 814zjvRY3SC4Mo4mtzguRvNu0styaUpemvRw5FDYK48GpEjg2eVxTnAFD4nr7ud0 # dhw3iaHP+RjA6s3EpPUqQ5nlZEgFJ+Tvkckk3wKSpksBYA4tJra6Uey5kpZ27x0T # KOzB2P6w+9B/B11n/aeSxvRPZdnXt2MyfS/3pwwfoFYioEyaEQ3Ie6ooachtdSL3 # PEvnJVK0VVYbZQwBXJlycNLlK/D++s4AEwmnZ5GmvDFuXlkRO9YMy9Wa5TKJl7gz # 76Aw1KHsE03SyAPvH4bE7eGkIwhJOQ== # =6hXE # -----END PGP SIGNATURE----- # gpg: Signature made Tue 01 Nov 2022 09:49:39 EDT # gpg: using RSA key 6685AE99E75167BCAFC8DF35FBD0DB095A9E2A44 # gpg: Good signature from "Alex Bennée (Master Work Key) <alex.bennee@linaro.org>" [unknown] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 6685 AE99 E751 67BC AFC8 DF35 FBD0 DB09 5A9E 2A44 * tag 'pull-testing-for-7.2-011122-3' of https://github.com/stsquad/qemu: (31 commits) tests/vm: use -o IdentitiesOnly=yes for ssh tests/unit: cleanups for test-io-channel-command contrib/plugins: protect execlog's last_exec expansion contrib/plugins: enable debug on CONFIG_DEBUG_TCG tests/tcg: include CONFIG_PLUGIN in config-host.mak target/s390x: fake instruction loading when handling 'ex' target/s390x: don't probe next pc for EXecuted insns target/s390x: don't use ld_code2 to probe next pc tests/tcg: re-enable threadcount for sh4 tests/tcg: re-enable linux-test for sh4 tests/avocado: disable sh4 rd2 tests on Gitlab tests/avocado: raspi2_initrd: Wait for guest shutdown message before stopping tests/avocado: set -machine none for userfwd and vnc tests MAINTAINERS: fix-up for check-tcg Makefile changes MAINTAINERS: add features_to_c.sh to gdbstub files MAINTAINERS: add entries for the key build bits hw/usb: dev-mtp: Use g_mkdir() block/vvfat: Unify the mkdir() call tcg: Avoid using hardcoded /tmp semihosting/arm-compat-semi: Avoid using hardcoded /tmp ... Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2022-11-01tests/tcg/multiarch: Add munmap-pthread.cIlya Leoshkevich2-0/+82
Add a test to detect races between munmap() and creating new threads. Signed-off-by: Ilya Leoshkevich <iii@linux.ibm.com> Message-Id: <20221028124227.2354792-3-iii@linux.ibm.com> [rth: add more return insns] Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2022-10-31tests/tcg: re-enable threadcount for sh4Alex Bennée1-6/+0
This test was marked as broken due to bug #856 which was fixed by ab419fd8a0 (target/sh4: Fix TB_FLAG_UNALIGN). Local testing shows this is solid now so lets re-enable the test. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Cc: Yoshinori Sato <ysato@users.sourceforge.jp> Message-Id: <20221027183637.2772968-23-alex.bennee@linaro.org>
2022-10-31tests/tcg: re-enable linux-test for sh4Alex Bennée1-6/+0
This test was marked as broken due to bug #704 which was fixed by aee14c77f4 (linux-user: Rewrite do_getdents, do_getdents64). Local testing shows this is solid now so lets re-enable the test. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Cc: Yoshinori Sato <ysato@users.sourceforge.jp> Message-Id: <20221027183637.2772968-22-alex.bennee@linaro.org>
2022-10-31tests/tcg/nios2: Tweak 10m50-ghrd.ldRichard Henderson1-5/+9
More closely follow the default linker script for nios2. This magically fixes a problem resolving .got relocs from the toolchain's libgcc.a. Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1258 Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20221024035341.2971123-1-richard.henderson@linaro.org> Message-Id: <20221027183637.2772968-10-alex.bennee@linaro.org>
2022-10-31tests/tcg: use regular semihosting for nios2-softmmuAlex Bennée1-2/+1
The nios2 code now plugs into the common semihosting code so we can use the same redirect invocation as the other boards. There is however a bug raised for the fact the tests don't seem to be completing properly and silently passing anyway: https://gitlab.com/qemu-project/qemu/-/issues/1258 Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20221027183637.2772968-9-alex.bennee@linaro.org>
2022-10-28tests/tcg/s390x: Add a test for the vistr instructionThomas Huth2-0/+49
This test can be used to verify that the change in the previous commit is indeed fixing the problem with the M3 vs. M4 field mixup. Message-Id: <20221012182755.1014853-4-thuth@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: David Hildenbrand <david@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
2022-10-27tests/tcg/s390x: Test compiler flags only once, not every timeThomas Huth1-10/+17
This is common practice, see the Makefile.target in the aarch64 folder for example. Suggested-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20221012182755.1014853-2-thuth@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: David Hildenbrand <david@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
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