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2018-12-11Fixes i386 xchgq testfabrice.desclaux@cea.fr1-1/+1
As "xchg" reads and writes both operands, the "+m" is required to avoid undefined behavior on -O2 compilation. Signed-off-by: Fabrice Desclaux <fabrice.desclaux@cea.fr> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <03506cf0-a204-f619-8ee4-4990a5e69af5@cea.fr> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2018-11-14tests/tcg/multiarch: fix 32bit linux-test on 64bit hostLaurent Vivier1-2/+2
Fix: TEST linux-test on i386 .../tests/tcg/multiarch/linux-test.c:201: readdir readdir() calls getdents64() to have the list of the entries in a directory, and getdents64() can return 64bit d_off values (with ext4, for instance) that will not fit in the 32bit d_off field of the readdir() dirent structure. To avoid that, use readdir64() to use a 64bit d_off field too. Signed-off-by: Laurent Vivier <laurent@vivier.eu> Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
2018-10-26tests: Fix typos in comments and help message (found by codespell)Stefan Weil3-3/+3
Fix also a grammar issue. Signed-off-by: Stefan Weil <sw@weilnetz.de> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20180713054755.23323-1-sw@weilnetz.de> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2018-10-26tests/tcg/README: fix location for lm32 testsCleber Rosa1-1/+1
Point to the right and obvious location for lm32 tests. Signed-off-by: Cleber Rosa <crosa@redhat.com> Reviewed-by: Thomas Huth <thuth@redhat.com> Acked-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20181004161852.11673-3-crosa@redhat.com> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2018-10-24tests/tcg/mips: Add tests for R5900 DIVU1Fredrik Noring2-0/+49
Add a test for DIVU1. Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: Fredrik Noring <noring@nocrew.org> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
2018-10-24tests/tcg/mips: Add tests for R5900 DIV1Fredrik Noring2-1/+75
Add a test for DIV1. Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: Fredrik Noring <noring@nocrew.org> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
2018-10-24tests/tcg/mips: Add tests for R5900 MTLO1 and MTHI1Fredrik Noring2-0/+41
Add a test for MTLO1 and MTHI1. Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: Fredrik Noring <noring@nocrew.org> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
2018-10-24tests/tcg/mips: Add tests for R5900 MFLO1 and MFHI1Fredrik Noring2-1/+37
Add a test for MFLO1 and MFHI1. Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: Fredrik Noring <noring@nocrew.org> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
2018-10-24tests/tcg/mips: Add tests for R5900 three-operand MULTU1Fredrik Noring1-7/+36
Add a test for MULTU1. Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: Fredrik Noring <noring@nocrew.org> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
2018-10-24tests/tcg/mips: Add tests for R5900 three-operand MULT1Fredrik Noring1-8/+37
Add a test for MULT1. Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: Fredrik Noring <noring@nocrew.org> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
2018-10-24tests/tcg/mips: Add tests for R5900 three-operand MULTUFredrik Noring2-0/+40
Add a test for MULTU. Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: Fredrik Noring <noring@nocrew.org> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
2018-10-24tests/tcg/mips: Add tests for R5900 three-operand MULTFredrik Noring2-0/+72
Add a test for MULT. Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: Fredrik Noring <noring@nocrew.org> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
2018-09-25Merge remote-tracking branch 'remotes/xtensa/tags/20180918-xtensa' into stagingPeter Maydell4-15/+163
target/xtensa updates: - fix gdbstub register counts; - add big-endian core test_kc705_be; - convert to do_transaction_failed and add test for failed memory transactions; - fix couple FPU2000 bugs; - fix s32c1i implementation; - clean up exception handlers generation in xtensa tests; - add support for semihosting console input through a chardev. # gpg: Signature made Tue 18 Sep 2018 18:35:50 BST # gpg: using RSA key 51F9CC91F83FA044 # gpg: Good signature from "Max Filippov <filippov@cadence.com>" # gpg: aka "Max Filippov <max.filippov@cogentembedded.com>" # gpg: aka "Max Filippov <jcmvbkbc@gmail.com>" # Primary key fingerprint: 2B67 854B 98E5 327D CDEB 17D8 51F9 CC91 F83F A044 * remotes/xtensa/tags/20180918-xtensa: target/xtensa: support input from chardev console target/xtensa: fix s32c1i TCGMemOp flags tests/tcg/xtensa: only generate defined exception handlers tests/tcg/xtensa: move exception handlers to separate section target/xtensa: fix FPU2000 bugs tests/tcg/xtensa: add test for failed memory transactions target/xtensa: convert to do_transaction_failed target/xtensa: add test_kc705_be core target/xtensa: clean up gdbstub register handling target/xtensa: fix gdbstub register counts Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-09-17tests/tcg/xtensa: only generate defined exception handlersMax Filippov1-0/+16
Don't generate handlers for IRQ levels that are not defined for the CPU or for window overflow/underflow exceptions for configs w/o windowed registers. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2018-09-17tests/tcg/xtensa: move exception handlers to separate sectionMax Filippov1-15/+22
Not all CPU configurations may have enough space for handler code between exception/interrupt vectors. Leave jumps to the handlers at the vectors, but move all handlers past the vectors area. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2018-09-17tests/tcg/xtensa: add test for failed memory transactionsMax Filippov2-0/+125
Failed memory transactions should raise exceptions 14 (for fetch) or 15 (for load/store) with XEA2. Memory accesses that result in TLB miss followed by an attempt to load PTE from physical memory which fails should raise InstTLBMiss or LoadStoreTLBMiss with XEA2. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2018-08-28target/s390x: fix PACK reading 1 byte less and writing 1 byte morePavel Zbitskiy2-0/+22
PACK fails on the test from the Principles of Operation: F1F2F3F4 becomes 0000234C instead of 0001234C due to an off-by-one error. Furthermore, it overwrites one extra byte to the left of F1. If len_dest is 0, then we only want to flip the 1st byte and never loop over the rest. Therefore, the loop condition should be > and not >=. If len_src is 1, then we should flip the 1st byte and pack the 2nd. Since len_src is already decremented before the loop, the first condition should be >=, and not >. Likewise for len_src == 2 and the second condition. Signed-off-by: Pavel Zbitskiy <pavel.zbitskiy@gmail.com> Message-Id: <20180821025104.19604-7-pavel.zbitskiy@gmail.com> Reviewed-by: David Hildenbrand <david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2018-08-28target/s390x: add EX support for TRT and TRTRPavel Zbitskiy3-0/+98
Improves "b213c9f5: target/s390x: Implement TRTR" by introducing the intermediate functions, which are compatible with dx_helper type. Signed-off-by: Pavel Zbitskiy <pavel.zbitskiy@gmail.com> Message-Id: <20180821025104.19604-6-pavel.zbitskiy@gmail.com> Reviewed-by: David Hildenbrand <david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2018-08-28target/s390x: fix IPM polluting irrelevant bitsPavel Zbitskiy2-0/+23
Suppose psw.mask=0x0000000080000000, cc=2, r1=0 and we do "ipm 1". This command must touch only bits 32-39, so the expected output is r1=0x20000000. However, currently qemu yields r1=0x20008000, because irrelevant parts of PSW leak into r1 during program mask transfer. Signed-off-by: Pavel Zbitskiy <pavel.zbitskiy@gmail.com> Message-Id: <20180821025104.19604-5-pavel.zbitskiy@gmail.com> Reviewed-by: David Hildenbrand <david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2018-08-28target/s390x: fix CSST decoding and runtime alignment checkPavel Zbitskiy2-0/+44
CSST is defined as: C(0xc802, CSST, SSF, CASS, la1, a2, 0, 0, csst, 0) It means that the first parameter is handled by in1_la1(). in1_la1() fills addr1 field, and not in1. Furthermore, when extract32() is used for the alignment check, the third parameter should specify the number of trailing bits that must be 0. For FC these numbers are: FC=0 (word, 4 bytes): 2 FC=1 (double word, 8 bytes): 3 FC=2 (quad word, 16 bytes): 4 For SC these numbers correspond to the size: SC=0: 0 SC=1: 1 SC=2: 2 SC=3: 3 SC=4: 4 Signed-off-by: Pavel Zbitskiy <pavel.zbitskiy@gmail.com> Message-Id: <20180821025104.19604-4-pavel.zbitskiy@gmail.com> Reviewed-by: David Hildenbrand <david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2018-08-28tests/tcg: add a simple s390x testPavel Zbitskiy2-0/+10
Copied from alpha. Signed-off-by: Pavel Zbitskiy <pavel.zbitskiy@gmail.com> Message-Id: <20180821025104.19604-2-pavel.zbitskiy@gmail.com> Reviewed-by: Thomas Huth <thuth@redhat.com> Reviewed-by: David Hildenbrand <david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2018-07-31tests: add check_invalid_maps to test-mmapAlex Bennée1-1/+21
This adds a test to make sure we fail properly for a 0 length mmap. There are most likely other failure conditions we should also check. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Cc: umarcor <1783362@bugs.launchpad.net> Message-Id: <20180730134321.19898-3-alex.bennee@linaro.org> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2018-07-24tests/tcg: remove runcom testAlex Bennée4-200/+0
The combination of being rather esoteric and needing to support mmap @ 0 means this only ever worked under translation. It has now regressed even further and is no longer useful. Kill it. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
2018-06-20tests: add top-level make dependency for docker buildsAlex Bennée1-0/+31
One problem with satisfying your docker dependencies in a sub-make it you might end up trying to satisfy the dependency multiple times. This is especially a problem with debian-sid based cross compilers and CI setups. We solve this by doing a docker build pass at the top level before any sub-makes are called. We still need to satisfy dependencies in the Makefile.target call so people can run tests from individual target directories. We introduce a new Makefile.probe which gets called for each PROBE_TARGET and allows us to build up the list. It does require multiply including config-target.mak which shouldn't cause any issues as it shouldn't define anything that clashes with config-host.mak. However we undefine a few key variables each time around. Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
2018-06-20tests/tcg/i386: extend timeout for runcom testAlex Bennée1-0/+1
The Travis hardware can be a little slow and the runcom test is fairly heavy in calculating pi. Lets double the timeout so we don't trip up during CI by mistake. Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
2018-06-20tests/tcg: override runners for broken testsAlex Bennée2-1/+9
To get a clean run of check-tcg these tests are currently skipped: - hello-mips for mips - linux-test for sparc Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2018-06-20tests/tcg: add run, diff, and skip helper macrosAlex Bennée5-19/+20
As we aren't using the default runners for all the test cases it is easy to miss out things like timeouts. To help with this we add some helpers and use them so we only need to make core changes in one place. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2018-06-20Makefile.target: add (clean-/build-)guest-tests targetsAlex Bennée1-0/+88
Now all the build infrastructure is in place we can build tests for each guest that we support. That support mainly depends on having cross compilers installed or docker setup. To keep all the logic for that together we put the rules in tests/tcg/Makefile.include and include it from the main Makefile.target. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2018-06-20tests/tcg/Makefile: update to be called from Makefile.targetAlex Bennée1-107/+76
This make is now invoked from each individual target make with the appropriate CC and EXTRA_CFLAGS set for each guest. It then includes additional Makefile.targets from: - tests/tcg/multiarch (always) - tests/tcg/$(TARGET_BASE_ARCH) (if available) - tests/tcg/$(TARGET_NAME) The order is important as the later Makefile's may want to suppress TESTS from its base arch profile. Each included Makefile.target is responsible for adding TESTS as well as defining any special build instructions for individual tests. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2018-06-20tests/tcg: enable building for PowerPCAlex Bennée3-2/+19
Now we have restored debian-image-powerpc-cross using Debian SID compilers we can build for 32 bit powerpc. Although PPC32 supports a range of pages sizes currently only 4k works so the others are commented out for now. We can also merge the ppc64 support under the base architecture directory to avoid too much proliferation of directories. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2018-06-20tests/tcg: enable building for RISCV64Alex Bennée1-0/+10
As before, using Debian SID compilers. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2018-06-20tests/tcg: enable building for mips64Alex Bennée1-0/+3
As before, using Debian SID compilers. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2018-06-20tests/tcg: enable building for sparc64Alex Bennée2-0/+8
As before, using Debian SID compilers. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2018-06-20tests/tcg: enable building for sh4Alex Bennée2-0/+11
As before, using Debian SID compilers. While the compiler can be coerced into generating big-endian code it seems the linker can't deal with it so we only enable the building for little endian SH4. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2018-06-20tests/tcg: enable building for m68kAlex Bennée2-0/+9
As before, using Debian SID compilers. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2018-06-20tests/tcg: enable building for HPPAAlex Bennée2-0/+8
Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2018-06-20tests/tcg/alpha: add Alpha specific testsAlex Bennée6-61/+17
These tests did use their own crt.o stub however that is a little stone age so we drop crt.S and just statically link to the cross compilers libraries. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2018-06-20tests/tcg: enable building for AlphaAlex Bennée2-0/+8
We can't use our normal Debian based compilers as Alpha isn't an officially supported architecture. However it is available as a port and fortunately cross compilers for all these targets are included in Debian Sid, the perpetual rolling/unstable/testing version of Debian. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2018-06-20tests/tcg: enable building for ppc64Alex Bennée1-0/+2
Currently this just enables building the multiarch tests. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2018-06-20tests/tcg: enable building for s390xAlex Bennée1-0/+2
This doesn't add any additional tests but enables building the multiarch tests for s390x. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Acked-by: Cornelia Huck <cohuck@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: David Hildenbrand <david@redhat.com>
2018-06-20tests/tcg/mips: include common mips hello-mipsAlex Bennée1-0/+19
Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2018-06-20tests/tcg: enable building for MIPSAlex Bennée1-0/+17
This doesn't add any additional tests but enables building the multiarch tests for MIPS using docker cross compilers. We don't have a cross compiler for mips64 big endian though. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2018-06-20tests/tcg: move MIPS specific tests into subdirAlex Bennée3-11/+7
These only need to be built for MIPS guests. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2018-06-20tests/tcg/arm: add fcvt test cases for AArch32/64Alex Bennée5-1/+7027
This runs through the usual float to float conversions and crucially also runs with ARM Alternative Half Precision Format. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2018-06-20tests/tcg: enable building for AArch64Alex Bennée1-0/+8
We only have compilers for the (default) little endian variants. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2018-06-20tests/tcg/arm: fix up test-arm-iwmmxt testAlex Bennée2-0/+5
We need to rename the source file to a .S so we can do a single-line assemble and link invocation. We also specify the additional CFLAGS for the compile as it's a non-standard ARM binary. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> [rth: force fpu configuration] Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
2018-06-20tests/tcg: enable building for ARMAlex Bennée2-1/+12
This allows us to use the docker cross compiler image to build these tests. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2018-06-20tests/tcg: move ARM specific tests into subdirAlex Bennée5-9/+24
These only need to be built for ARM guests. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
2018-06-20tests/tcg/i386/test-i386: fix printf formatAlex Bennée1-1/+1
Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2018-06-20tests/tcg/i386/test-i386: use modern vector_size attributesAlex Bennée1-2/+2
The compiler complains about the old __mode__ style attributes. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
generated by cgit v1.1 at 2024-11-01 21:41:31 +0000