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2023-11-07tests: bios-tables-test: Prepare the ACPI table change for smbios type4 core ↵Zhao Liu1-0/+3
count test Following the guidelines in tests/qtest/bios-tables-test.c, this is step 1 - 3. List the ACPI tables that will be added to test the type 4 core count field. Signed-off-by: Zhao Liu <zhao1.liu@intel.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Message-Id: <20231023094635.1588282-6-zhao1.liu@linux.intel.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2023-11-07tests: bios-tables-test: Add ACPI table binaries for smbios type4 count testZhao Liu1-3/+0
Following the guidelines in tests/qtest/bios-tables-test.c, this is step 5 and 6. Changes in the tables: FACP: +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20200925 (64-bit version) + * Copyright (c) 2000 - 2020 Intel Corporation + * + * Disassembly of /tmp/aml-W37791, Wed Aug 23 10:36:32 2023 + * + * ACPI Data Table [FACP] + * + * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue + */ + +[000h 0000 4] Signature : "FACP" [Fixed ACPI Description Table (FADT)] +[004h 0004 4] Table Length : 000000F4 +[008h 0008 1] Revision : 03 +[009h 0009 1] Checksum : B3 +[00Ah 0010 6] Oem ID : "BOCHS " +[010h 0016 8] Oem Table ID : "BXPC " +[018h 0024 4] Oem Revision : 00000001 +[01Ch 0028 4] Asl Compiler ID : "BXPC" +[020h 0032 4] Asl Compiler Revision : 00000001 + +[024h 0036 4] FACS Address : 00000000 +[028h 0040 4] DSDT Address : 00000000 +[02Ch 0044 1] Model : 01 +[02Dh 0045 1] PM Profile : 00 [Unspecified] +[02Eh 0046 2] SCI Interrupt : 0009 +[030h 0048 4] SMI Command Port : 000000B2 +[034h 0052 1] ACPI Enable Value : 02 +[035h 0053 1] ACPI Disable Value : 03 +[036h 0054 1] S4BIOS Command : 00 +[037h 0055 1] P-State Control : 00 +[038h 0056 4] PM1A Event Block Address : 00000600 +[03Ch 0060 4] PM1B Event Block Address : 00000000 +[040h 0064 4] PM1A Control Block Address : 00000604 +[044h 0068 4] PM1B Control Block Address : 00000000 +[048h 0072 4] PM2 Control Block Address : 00000000 +[04Ch 0076 4] PM Timer Block Address : 00000608 +[050h 0080 4] GPE0 Block Address : 00000620 +[054h 0084 4] GPE1 Block Address : 00000000 +[058h 0088 1] PM1 Event Block Length : 04 +[059h 0089 1] PM1 Control Block Length : 02 +[05Ah 0090 1] PM2 Control Block Length : 00 +[05Bh 0091 1] PM Timer Block Length : 04 +[05Ch 0092 1] GPE0 Block Length : 10 +[05Dh 0093 1] GPE1 Block Length : 00 +[05Eh 0094 1] GPE1 Base Offset : 00 +[05Fh 0095 1] _CST Support : 00 +[060h 0096 2] C2 Latency : 0FFF +[062h 0098 2] C3 Latency : 0FFF +[064h 0100 2] CPU Cache Size : 0000 +[066h 0102 2] Cache Flush Stride : 0000 +[068h 0104 1] Duty Cycle Offset : 00 +[069h 0105 1] Duty Cycle Width : 00 +[06Ah 0106 1] RTC Day Alarm Index : 00 +[06Bh 0107 1] RTC Month Alarm Index : 00 +[06Ch 0108 1] RTC Century Index : 32 +[06Dh 0109 2] Boot Flags (decoded below) : 0002 + Legacy Devices Supported (V2) : 0 + 8042 Present on ports 60/64 (V2) : 1 + VGA Not Present (V4) : 0 + MSI Not Supported (V4) : 0 + PCIe ASPM Not Supported (V4) : 0 + CMOS RTC Not Present (V5) : 0 +[06Fh 0111 1] Reserved : 00 +[070h 0112 4] Flags (decoded below) : 000484A5 + WBINVD instruction is operational (V1) : 1 + WBINVD flushes all caches (V1) : 0 + All CPUs support C1 (V1) : 1 + C2 works on MP system (V1) : 0 + Control Method Power Button (V1) : 0 + Control Method Sleep Button (V1) : 1 + RTC wake not in fixed reg space (V1) : 0 + RTC can wake system from S4 (V1) : 1 + 32-bit PM Timer (V1) : 0 + Docking Supported (V1) : 0 + Reset Register Supported (V2) : 1 + Sealed Case (V3) : 0 + Headless - No Video (V3) : 0 + Use native instr after SLP_TYPx (V3) : 0 + PCIEXP_WAK Bits Supported (V4) : 0 + Use Platform Timer (V4) : 1 + RTC_STS valid on S4 wake (V4) : 0 + Remote Power-on capable (V4) : 0 + Use APIC Cluster Model (V4) : 1 + Use APIC Physical Destination Mode (V4) : 0 + Hardware Reduced (V5) : 0 + Low Power S0 Idle (V5) : 0 + +[074h 0116 12] Reset Register : [Generic Address Structure] +[074h 0116 1] Space ID : 01 [SystemIO] +[075h 0117 1] Bit Width : 08 +[076h 0118 1] Bit Offset : 00 +[077h 0119 1] Encoded Access Width : 00 [Undefined/Legacy] +[078h 0120 8] Address : 0000000000000CF9 + +[080h 0128 1] Value to cause reset : 0F +[081h 0129 2] ARM Flags (decoded below) : 0000 + PSCI Compliant : 0 + Must use HVC for PSCI : 0 + +[083h 0131 1] FADT Minor Revision : 00 +[084h 0132 8] FACS Address : 0000000000000000 +[08Ch 0140 8] DSDT Address : 0000000000000000 +[094h 0148 12] PM1A Event Block : [Generic Address Structure] +[094h 0148 1] Space ID : 01 [SystemIO] +[095h 0149 1] Bit Width : 20 +[096h 0150 1] Bit Offset : 00 +[097h 0151 1] Encoded Access Width : 00 [Undefined/Legacy] +[098h 0152 8] Address : 0000000000000600 + +[0A0h 0160 12] PM1B Event Block : [Generic Address Structure] +[0A0h 0160 1] Space ID : 00 [SystemMemory] +[0A1h 0161 1] Bit Width : 00 +[0A2h 0162 1] Bit Offset : 00 +[0A3h 0163 1] Encoded Access Width : 00 [Undefined/Legacy] +[0A4h 0164 8] Address : 0000000000000000 + +[0ACh 0172 12] PM1A Control Block : [Generic Address Structure] +[0ACh 0172 1] Space ID : 01 [SystemIO] +[0ADh 0173 1] Bit Width : 10 +[0AEh 0174 1] Bit Offset : 00 +[0AFh 0175 1] Encoded Access Width : 00 [Undefined/Legacy] +[0B0h 0176 8] Address : 0000000000000604 + +[0B8h 0184 12] PM1B Control Block : [Generic Address Structure] +[0B8h 0184 1] Space ID : 00 [SystemMemory] +[0B9h 0185 1] Bit Width : 00 +[0BAh 0186 1] Bit Offset : 00 +[0BBh 0187 1] Encoded Access Width : 00 [Undefined/Legacy] +[0BCh 0188 8] Address : 0000000000000000 + +[0C4h 0196 12] PM2 Control Block : [Generic Address Structure] +[0C4h 0196 1] Space ID : 00 [SystemMemory] +[0C5h 0197 1] Bit Width : 00 +[0C6h 0198 1] Bit Offset : 00 +[0C7h 0199 1] Encoded Access Width : 00 [Undefined/Legacy] +[0C8h 0200 8] Address : 0000000000000000 + +[0D0h 0208 12] PM Timer Block : [Generic Address Structure] +[0D0h 0208 1] Space ID : 01 [SystemIO] +[0D1h 0209 1] Bit Width : 20 +[0D2h 0210 1] Bit Offset : 00 +[0D3h 0211 1] Encoded Access Width : 00 [Undefined/Legacy] +[0D4h 0212 8] Address : 0000000000000608 + +[0DCh 0220 12] GPE0 Block : [Generic Address Structure] +[0DCh 0220 1] Space ID : 01 [SystemIO] +[0DDh 0221 1] Bit Width : 80 +[0DEh 0222 1] Bit Offset : 00 +[0DFh 0223 1] Encoded Access Width : 00 [Undefined/Legacy] +[0E0h 0224 8] Address : 0000000000000620 + +[0E8h 0232 12] GPE1 Block : [Generic Address Structure] +[0E8h 0232 1] Space ID : 00 [SystemMemory] +[0E9h 0233 1] Bit Width : 00 +[0EAh 0234 1] Bit Offset : 00 +[0EBh 0235 1] Encoded Access Width : 00 [Undefined/Legacy] +[0ECh 0236 8] Address : 0000000000000000 + ... APIC: +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20200925 (64-bit version) + * Copyright (c) 2000 - 2020 Intel Corporation + * + * Disassembly of /tmp/aml-687791, Wed Aug 23 10:36:32 2023 + * + * ACPI Data Table [APIC] + * + * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue + */ + +[000h 0000 4] Signature : "APIC" [Multiple APIC Description Table (MADT)] +[004h 0004 4] Table Length : 00000430 +[008h 0008 1] Revision : 03 +[009h 0009 1] Checksum : C5 +[00Ah 0010 6] Oem ID : "BOCHS " +[010h 0016 8] Oem Table ID : "BXPC " +[018h 0024 4] Oem Revision : 00000001 +[01Ch 0028 4] Asl Compiler ID : "BXPC" +[020h 0032 4] Asl Compiler Revision : 00000001 + +[024h 0036 4] Local Apic Address : FEE00000 +[028h 0040 4] Flags (decoded below) : 00000001 + PC-AT Compatibility : 1 + +[02Ch 0044 1] Subtable Type : 00 [Processor Local APIC] +[02Dh 0045 1] Length : 08 +[02Eh 0046 1] Processor ID : 00 +[02Fh 0047 1] Local Apic ID : 00 +[030h 0048 4] Flags (decoded below) : 00000001 + Processor Enabled : 1 + Runtime Online Capable : 0 + +[034h 0052 1] Subtable Type : 00 [Processor Local APIC] +[035h 0053 1] Length : 08 +[036h 0054 1] Processor ID : 01 +[037h 0055 1] Local Apic ID : 01 +[038h 0056 4] Flags (decoded below) : 00000001 + Processor Enabled : 1 + Runtime Online Capable : 0 [snip] +[3E4h 0996 1] Subtable Type : 00 [Processor Local APIC] +[3E5h 0997 1] Length : 08 +[3E6h 0998 1] Processor ID : 77 +[3E7h 0999 1] Local Apic ID : 9E +[3E8h 1000 4] Flags (decoded below) : 00000000 + Processor Enabled : 0 + Runtime Online Capable : 0 + +[3ECh 1004 1] Subtable Type : 01 [I/O APIC] +[3EDh 1005 1] Length : 0C +[3EEh 1006 1] I/O Apic ID : 00 +[3EFh 1007 1] Reserved : 00 +[3F0h 1008 4] Address : FEC00000 +[3F4h 1012 4] Interrupt : 00000000 + +[3F8h 1016 1] Subtable Type : 02 [Interrupt Source Override] +[3F9h 1017 1] Length : 0A +[3FAh 1018 1] Bus : 00 +[3FBh 1019 1] Source : 00 +[3FCh 1020 4] Interrupt : 00000002 +[400h 1024 2] Flags (decoded below) : 0000 + Polarity : 0 + Trigger Mode : 0 + +[402h 1026 1] Subtable Type : 02 [Interrupt Source Override] +[403h 1027 1] Length : 0A +[404h 1028 1] Bus : 00 +[405h 1029 1] Source : 05 +[406h 1030 4] Interrupt : 00000005 +[40Ah 1034 2] Flags (decoded below) : 000D + Polarity : 1 + Trigger Mode : 3 + +[40Ch 1036 1] Subtable Type : 02 [Interrupt Source Override] +[40Dh 1037 1] Length : 0A +[40Eh 1038 1] Bus : 00 +[40Fh 1039 1] Source : 09 +[410h 1040 4] Interrupt : 00000009 +[414h 1044 2] Flags (decoded below) : 000D + Polarity : 1 + Trigger Mode : 3 + +[416h 1046 1] Subtable Type : 02 [Interrupt Source Override] +[417h 1047 1] Length : 0A +[418h 1048 1] Bus : 00 +[419h 1049 1] Source : 0A +[41Ah 1050 4] Interrupt : 0000000A +[41Eh 1054 2] Flags (decoded below) : 000D + Polarity : 1 + Trigger Mode : 3 + +[420h 1056 1] Subtable Type : 02 [Interrupt Source Override] +[421h 1057 1] Length : 0A +[422h 1058 1] Bus : 00 +[423h 1059 1] Source : 0B +[424h 1060 4] Interrupt : 0000000B +[428h 1064 2] Flags (decoded below) : 000D + Polarity : 1 + Trigger Mode : 3 + +[42Ah 1066 1] Subtable Type : 04 [Local APIC NMI] +[42Bh 1067 1] Length : 06 +[42Ch 1068 1] Processor ID : FF +[42Dh 1069 2] Flags (decoded below) : 0000 + Polarity : 0 + Trigger Mode : 0 +[42Fh 1071 1] Interrupt Input LINT : 01 + ... DSDT: +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20200925 (64-bit version) + * Copyright (c) 2000 - 2020 Intel Corporation + * + * Disassembling to symbolic ASL+ operators + * + * Disassembly of /tmp/aml-8G8791, Wed Aug 23 10:36:32 2023 + * + * Original Table Header: + * Signature "DSDT" + * Length 0x0000489D (18589) + * Revision 0x01 **** 32-bit table (V1), no 64-bit math support + * Checksum 0xDB + * OEM ID "BOCHS " + * OEM Table ID "BXPC " + * OEM Revision 0x00000001 (1) + * Compiler ID "BXPC" + * Compiler Version 0x00000001 (1) + */ +DefinitionBlock ("", "DSDT", 1, "BOCHS ", "BXPC ", 0x00000001) +{ + Scope (\) + { + OperationRegion (DBG, SystemIO, 0x0402, One) + Field (DBG, ByteAcc, NoLock, Preserve) + { + DBGB, 8 + } + + Method (DBUG, 1, NotSerialized) + { + ToHexString (Arg0, Local0) + ToBuffer (Local0, Local0) + Local1 = (SizeOf (Local0) - One) + Local2 = Zero + While ((Local2 < Local1)) + { + DBGB = DerefOf (Local0 [Local2]) + Local2++ + } + + DBGB = 0x0A + } + } + [snip] + + Processor (C000, 0x00, 0x00000000, 0x00) + { + Method (_STA, 0, Serialized) // _STA: Status + { + Return (CSTA (Zero)) + } + + Name (_MAT, Buffer (0x08) // _MAT: Multiple APIC Table Entry + { + 0x00, 0x08, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00 // ........ + }) + Method (_OST, 3, Serialized) // _OST: OSPM Status Indication + { + COST (Zero, Arg0, Arg1, Arg2) + } + } + + Processor (C001, 0x01, 0x00000000, 0x00) + { + Method (_STA, 0, Serialized) // _STA: Status + { + Return (CSTA (One)) + } + + Name (_MAT, Buffer (0x08) // _MAT: Multiple APIC Table Entry + { + 0x00, 0x08, 0x01, 0x01, 0x01, 0x00, 0x00, 0x00 // ........ + }) + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + CEJ0 (One) + } + + Method (_OST, 3, Serialized) // _OST: OSPM Status Indication + { + COST (One, Arg0, Arg1, Arg2) + } + } [snip] + Processor (C077, 0x77, 0x00000000, 0x00) + { + Method (_STA, 0, Serialized) // _STA: Status + { + Return (CSTA (0x77)) + } + + Name (_MAT, Buffer (0x08) // _MAT: Multiple APIC Table Entry + { + 0x00, 0x08, 0x77, 0x9E, 0x01, 0x00, 0x00, 0x00 // ..w..... + }) + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + CEJ0 (0x77) + } + + Method (_OST, 3, Serialized) // _OST: OSPM Status Indication + { + COST (0x77, Arg0, Arg1, Arg2) + } + } + } + } + ... Signed-off-by: Zhao Liu <zhao1.liu@intel.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Message-Id: <20231023094635.1588282-5-zhao1.liu@linux.intel.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2023-11-07tests: bios-tables-test: Add test for smbios type4 countZhao Liu1-1/+32
This tests the commit d79a284a44bb7 ("hw/smbios: Fix smbios_smp_sockets calculation"). In smbios_get_tables() (hw/smbios/smbios.c), smbios type4 table is built for each socket, so the count of type4 tables should be equal to the number of sockets. Thus for the topology in this case, there're the following considerations: 1. The topology should include multiple sockets to ensure smbios could create type4 tables for each socket. 2. In addition to sockets, for the more general topology, we should also configure as many topology levels as possible (multiple dies, no module since x86 hasn't supported it), to ensure that smbios is able to exclude the effect of other topology levels to create the type4 tables only for sockets. 3. The original miscalculation bug also misused "smp.cpus", so it's necessary to configure "cpus" (presented threads for machine) and "maxcpus" (total threads for machine) as well to make sure that configuring unpluged CPUs in smp (cpus < maxcpus) does not affect the correctness of the count of type4 tables. Based on these considerations, select the topology as the follow: -smp cpus=100,maxcpus=120,sockets=5,dies=2,cores=4,threads=3 The expected count of type4 tables = sockets (5). Suggested-by: Igor Mammedov <imammedo@redhat.com> Signed-off-by: Zhao Liu <zhao1.liu@intel.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Message-Id: <20231023094635.1588282-4-zhao1.liu@linux.intel.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2023-11-07tests: bios-tables-test: Prepare the ACPI table change for smbios type4 ↵Zhao Liu1-0/+3
count test Following the guidelines in tests/qtest/bios-tables-test.c, this is step 1 - 3. List the ACPI tables that will be added to test the type 4 count. Signed-off-by: Zhao Liu <zhao1.liu@intel.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Message-Id: <20231023094635.1588282-3-zhao1.liu@linux.intel.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2023-11-07Merge tag 'pull-hv-balloon-20231106' of ↵Stefan Hajnoczi1-0/+1
https://github.com/maciejsszmigiero/qemu into staging Hyper-V Dynamic Memory protocol driver. This driver is like virtio-balloon on steroids for Windows guests: it allows both changing the guest memory allocation via ballooning and inserting pieces of extra RAM into it on demand from a provided memory backend via Windows-native Hyper-V Dynamic Memory protocol. * Preparatory patches to support empty memory devices and ones with large alignment requirements. * Revert of recently added "hw/virtio/virtio-pmem: Replace impossible check by assertion" commit 5960f254dbb4 since this series makes this situation possible again. * Protocol definitions. * Hyper-V DM protocol driver (hv-balloon) base (ballooning only). * Hyper-V DM protocol driver (hv-balloon) hot-add support. * qapi query-memory-devices support for the driver. * qapi HV_BALLOON_STATUS_REPORT event. * The relevant PC machine plumbing. * New MAINTAINERS entry for the above. # -----BEGIN PGP SIGNATURE----- # # iQGzBAABCAAdFiEE4ndqq6COJv9aG0oJUrHW6VHQzgcFAmVI81IACgkQUrHW6VHQ # zgdzTgv+I5eV2R01YLOBBJhBjzxZ4/BUqkuUHNxHpfjuCqEIzPb7FIfoZ4ZyXZFT # YJdSE4lPeTZLrmmi/Nt6G0rUKDvdCeIgkS2VLHFSsTV8IzcT71BTRGzV0zAjUF5v # yDH6uzo6e9gmaziIalRjibUxSDjCQmoCifms2rS2DwazADudUp+naGfm+3uyA0gM # raOfBfRkNZsDqhXg2ayuqPIES75xQONoON9xYPKDAthS48POEbqtWBKuFopr3kXY # y0eph+NAw+RajCyLYKM3poIgaSu3l4WegInuKQffzqKR8dxrbwPdCmtgo6NSHx0W # uDfl7FUBnGzrR18VU4ZfTSrF5SVscGwF9EL7uocJen15inJjl1q3G53uZgyGzHLC # cw8fKMjucmE8njQR2qiMyX0b+T4+9nKO1rykBgTG/+c9prRUVoxYpFCF117Ei0U8 # QzLGACW1oK+LV41bekWAye7w9pShUtFaxffhPbJeZDDGh7q0x61R3Z3yKkA07p46 # /YWWFWUD # =RAb0 # -----END PGP SIGNATURE----- # gpg: Signature made Mon 06 Nov 2023 22:08:18 HKT # gpg: using RSA key E2776AABA08E26FF5A1B4A0952B1D6E951D0CE07 # gpg: Good signature from "Maciej S. Szmigiero <mail@maciej.szmigiero.name>" [unknown] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 727A 0D4D DB9E D9F6 039B ECEF 847F 5E37 90CE 0977 # Subkey fingerprint: E277 6AAB A08E 26FF 5A1B 4A09 52B1 D6E9 51D0 CE07 * tag 'pull-hv-balloon-20231106' of https://github.com/maciejsszmigiero/qemu: MAINTAINERS: Add an entry for Hyper-V Dynamic Memory Protocol hw/i386/pc: Support hv-balloon qapi: Add HV_BALLOON_STATUS_REPORT event and its QMP query command qapi: Add query-memory-devices support to hv-balloon Add Hyper-V Dynamic Memory Protocol driver (hv-balloon) hot-add support Add Hyper-V Dynamic Memory Protocol driver (hv-balloon) base Add Hyper-V Dynamic Memory Protocol definitions memory-device: Drop size alignment check Revert "hw/virtio/virtio-pmem: Replace impossible check by assertion" memory-device: Support empty memory devices Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2023-11-06qapi: Add HV_BALLOON_STATUS_REPORT event and its QMP query commandMaciej S. Szmigiero1-0/+1
Used by the hv-balloon driver for (optional) guest memory status reports. Acked-by: David Hildenbrand <david@redhat.com> Signed-off-by: Maciej S. Szmigiero <maciej.szmigiero@oracle.com>
2023-11-03tests: Add migration dirty-limit capability testHyman Huang1-0/+164
Add migration dirty-limit capability test if kernel support dirty ring. Migration dirty-limit capability introduce dirty limit capability, two parameters: x-vcpu-dirty-limit-period and vcpu-dirty-limit are introduced to implement the live migration with dirty limit. The test case does the following things: 1. start src, dst vm and enable dirty-limit capability 2. start migrate and set cancel it to check if dirty limit stop working. 3. restart dst vm 4. start migrate and enable dirty-limit capability 5. check if migration satisfy the convergence condition during pre-switchover phase. Note that this test case involves many passes, so it runs in slow mode only. Signed-off-by: Hyman Huang <yong.huang@smartx.com> Acked-by: Peter Xu <peterx@redhat.com> Reviewed-by: Fabiano Rosas <farosas@suse.de> Reviewed-by: Juan Quintela <quintela@redhat.com> Signed-off-by: Juan Quintela <quintela@redhat.com> Message-ID: <e55a302df9da7dbc00ad825f47f57c1a756d303e.1698847223.git.yong.huang@smartx.com>
2023-11-03Merge tag 'pull-target-arm-20231102' of ↵Stefan Hajnoczi2-1/+486
https://git.linaro.org/people/pmaydell/qemu-arm into staging target-arm queue: * linux-user/elfload: Add missing arm64 hwcap values * stellaris-gamepad: Convert to qdev * docs/specs: Convert various txt docs to rST * MAINTAINERS: Make sure that gicv3_internal.h is covered, too * hw/arm/pxa2xx_gpio: Pass CPU using QOM link property * hw/watchdog/wdt_imx2: Trace MMIO access and timer activity * hw/misc/imx7_snvs: Trace MMIO access * hw/misc/imx6_ccm: Convert DPRINTF to trace events * hw/i2c/pm_smbus: Convert DPRINTF to trace events * target/arm: Enable FEAT_MOPS insns in user-mode emulation * linux-user: Report AArch64 hwcap2 fields above bit 31 * target/arm: Make FEAT_MOPS SET* insns handle Xs == XZR correctly * target/arm: Fix SVE STR increment * hw/char/stm32f2xx_usart: implement TX interrupts * target/arm: Correctly propagate stage 1 BTI guarded bit in a two-stage walk * xlnx-versal-virt: Add AMD/Xilinx TRNG device * tag 'pull-target-arm-20231102' of https://git.linaro.org/people/pmaydell/qemu-arm: (33 commits) tests/qtest: Introduce tests for AMD/Xilinx Versal TRNG device hw/arm: xlnx-versal-virt: Add AMD/Xilinx TRNG device hw/misc: Introduce AMD/Xilix Versal TRNG device target/arm: Correctly propagate stage 1 BTI guarded bit in a two-stage walk hw/char/stm32f2xx_usart: Add more definitions for CR1 register hw/char/stm32f2xx_usart: Update IRQ when DR is written hw/char/stm32f2xx_usart: Extract common IRQ update code to update_irq() target/arm: Fix SVE STR increment target/arm: Make FEAT_MOPS SET* insns handle Xs == XZR correctly linux-user: Report AArch64 hwcap2 fields above bit 31 target/arm: Enable FEAT_MOPS insns in user-mode emulation hw/i2c/pm_smbus: Convert DPRINTF to trace events hw/misc/imx6_ccm: Convert DPRINTF to trace events hw/misc/imx7_snvs: Trace MMIO access hw/watchdog/wdt_imx2: Trace timer activity hw/watchdog/wdt_imx2: Trace MMIO access hw/arm/pxa2xx_gpio: Pass CPU using QOM link property MAINTAINERS: Make sure that gicv3_internal.h is covered, too docs/specs/vmgenid: Convert to rST docs/specs/vmcoreinfo: Convert to rST ... Conflicts: hw/input/stellaris_input.c The qdev conversion in this pull request ("stellaris-gamepad: Convert to qdev") eliminates the vmstate_register() call that was converted to vmstate_register_any() in the conflicting migration pull request. vmstate_register_any() is no longer necessary now that this device has been converted to qdev, so take this pull request's version of stellaris_gamepad.c over the previous pull request's stellaris_input.c (the file was renamed). Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2023-11-02tests/qtest: Introduce tests for AMD/Xilinx Versal TRNG deviceTong Ho2-1/+486
Signed-off-by: Tong Ho <tong.ho@amd.com> Message-id: 20231031184611.3029156-4-tong.ho@amd.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2023-11-02migration: modify test_multifd_tcp_none() to use new QAPI syntax.Het Gala1-1/+6
modify multifd tcp common test to incorporate the new QAPI syntax defined. Suggested-by: Aravind Retnakaran <aravind.retnakaran@nutanix.com> Signed-off-by: Het Gala <het.gala@nutanix.com> Signed-off-by: Fabiano Rosas <farosas@suse.de> Reviewed-by: Juan Quintela <quintela@redhat.com> Signed-off-by: Juan Quintela <quintela@redhat.com> Message-ID: <20231023182053.8711-15-farosas@suse.de>
2023-11-02tests/migration-test: Add a test for postcopy hangs during RECOVERFabiano Rosas1-6/+104
To do so, create two paired sockets, but make them not providing real data. Feed those fake sockets to src/dst QEMUs for recovery to let them go into RECOVER stage without going out. Test that we can always kick it out and recover again with the right ports. This patch is based on Fabiano's version here: https://lore.kernel.org/r/877cowmdu0.fsf@suse.de Signed-off-by: Fabiano Rosas <farosas@suse.de> [peterx: write commit message, remove case 1, fix bugs, and more] Signed-off-by: Peter Xu <peterx@redhat.com> Reviewed-by: Juan Quintela <quintela@redhat.com> Signed-off-by: Juan Quintela <quintela@redhat.com> Message-ID: <20231017202633.296756-4-peterx@redhat.com>
2023-11-02tests/qtest: migration: add reboot mode testSteve Sistare1-0/+33
[ Maintainer note: I put the test as flaky because our CI has problems with shared memory. We will remove the flaky bits as soon as we get a solution. ] Signed-off-by: Steve Sistare <steven.sistare@oracle.com> Reviewed-by: Juan Quintela <quintela@redhat.com> Signed-off-by: Juan Quintela <quintela@redhat.com> Message-ID: <1698263069-406971-7-git-send-email-steven.sistare@oracle.com>
2023-10-31Merge tag 'pull-ufs-20231030' of https://gitlab.com/jeuk20.kim/qemu into stagingStefan Hajnoczi1-9/+28
ufs-next-pull-request # -----BEGIN PGP SIGNATURE----- # # iQIzBAABCgAdFiEEUBfYMVl8eKPZB+73EuIgTA5dtgIFAmU/DfoACgkQEuIgTA5d # tgKZ3g/+J38LTaktLPgUb0Kg390anPkIAkqqA1QZC8lC/FRSEWpgsNBqcvAASNTl # jj1c80k/+Dvf9Ti1lmDNkuYczCFvKNJZQ1iRHmv2wc79A01GV0Ue6xayQjjNjoKK # SBMIsFpArmFQjR2wGlkRc8PXha1JyWrsD4iPY6ZqedEcyuueLx69XbLL37FfVbQt # 5IMnDqGkLCmrGowAjwurq2UM5IiYjeB4I5OwUgJC526zlyngXTFJimCWS6b2uUBk # Yg1PnFffBsh11Pwmq4IZ1DAv3Bv/gFovenuatFqZrgqtfK7tEiARInIEsctu0U0a # hPK/KojJAPF/cfMssRm1D1GCfsXM4tP2yFY/6q0wTRr9Dod8OSjlvfJR7+ez71/j # aoY4N/nYYrZ6+pQNsPJcuBqQdtjdNUp4gUHx5qYxwwqZcHK4ubxpIvstmxceoLEX # 3PG4O1iAapc/aL12ww9bYJ2lrbKGx7ZJU/Ij8bud8tYzLheG3xaYUEhonk7DE6+e # AXFSad5CJTIF9Duh1uAMe1sV9GxELV8MHZSalqfGOhWYp7LzUBgouEJ1gQdOQbTK # VsLs48WQ23OjWNKyAMaXQXdFO4FVbsjIg9nQXEHNRPkUownVHNVL8zu6EsXvHfch # u691ygt5pD100SYdcDv73xTSeqP/rxqyYdxJl4LRkv/hGWU4y78= # =Oisg # -----END PGP SIGNATURE----- # gpg: Signature made Mon 30 Oct 2023 10:59:22 JST # gpg: using RSA key 5017D831597C78A3D907EEF712E2204C0E5DB602 # gpg: Good signature from "Jeuk Kim <jeuk20.kim@samsung.com>" [unknown] # gpg: aka "Jeuk Kim <jeuk20.kim@gmail.com>" [unknown] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 5017 D831 597C 78A3 D907 EEF7 12E2 204C 0E5D B602 * tag 'pull-ufs-20231030' of https://gitlab.com/jeuk20.kim/qemu: hw/ufs: Modify lu.c to share codes with SCSI subsystem Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2023-10-30hw/ufs: Modify lu.c to share codes with SCSI subsystemJeuk Kim1-9/+28
This patch removes the code that ufs-lu was duplicating from scsi-hd and allows them to share code. It makes ufs-lu have a virtual scsi-bus and scsi-hd internally. This allows scsi related commands to be passed thorugh to the scsi-hd. The query request and nop command work the same as the existing logic. Well-known lus do not have a virtual scsi-bus and scsi-hd, and handle the necessary scsi commands by emulating them directly. Signed-off-by: Jeuk Kim <jeuk20.kim@samsung.com>
2023-10-27ipmi-bt-test: force ipv4Vladimir Sementsov-Ogievskiy1-1/+1
We open ipv4 listening socket. But "localhost" in qemu parameters may load to Qemu trying to connect with ipv6 and fail with "Connection refused". Force ipv4 by using ipv4 ip address. Signed-off-by: Vladimir Sementsov-Ogievskiy <vsementsov@yandex-team.ru> Message-ID: <20231018191123.1176602-1-vsementsov@yandex-team.ru> Acked-by: Corey Minyard <cminyard@mvista.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
2023-10-27tests/npcm7xx_adc: Clean up global variable shadowingPhilippe Mathieu-Daudé1-7/+7
Rename the global 'adc' variable in order to avoid: tests/qtest/npcm7xx_adc-test.c:98:58: error: declaration shadows a variable in the global scope [-Werror,-Wshadow] static uint32_t adc_read_con(QTestState *qts, const ADC *adc) ^ tests/qtest/npcm7xx_adc-test.c:103:55: error: declaration shadows a variable in the global scope [-Werror,-Wshadow] static void adc_write_con(QTestState *qts, const ADC *adc, uint32_t value) ^ tests/qtest/npcm7xx_adc-test.c:108:59: error: declaration shadows a variable in the global scope [-Werror,-Wshadow] static uint32_t adc_read_data(QTestState *qts, const ADC *adc) ^ tests/qtest/npcm7xx_adc-test.c:119:53: error: declaration shadows a variable in the global scope [-Werror,-Wshadow] static void adc_qom_set(QTestState *qts, const ADC *adc, ^ tests/qtest/npcm7xx_adc-test.c:135:57: error: declaration shadows a variable in the global scope [-Werror,-Wshadow] static void adc_write_input(QTestState *qts, const ADC *adc, ^ tests/qtest/npcm7xx_adc-test.c:144:56: error: declaration shadows a variable in the global scope [-Werror,-Wshadow] static void adc_write_vref(QTestState *qts, const ADC *adc, uint32_t value) ^ tests/qtest/npcm7xx_adc-test.c:162:59: error: declaration shadows a variable in the global scope [-Werror,-Wshadow] static uint32_t adc_prescaler(QTestState *qts, const ADC *adc) ^ tests/qtest/npcm7xx_adc-test.c:175:64: error: declaration shadows a variable in the global scope [-Werror,-Wshadow] static void adc_wait_conv_finished(QTestState *qts, const ADC *adc, ^ tests/qtest/npcm7xx_adc-test.c:196:16: error: declaration shadows a variable in the global scope [-Werror,-Wshadow] const ADC *adc = adc_p; ^ tests/qtest/npcm7xx_adc-test.c:207:16: error: declaration shadows a variable in the global scope [-Werror,-Wshadow] const ADC *adc = adc_p; ^ tests/qtest/npcm7xx_adc-test.c:235:16: error: declaration shadows a variable in the global scope [-Werror,-Wshadow] const ADC *adc = adc_p; ^ tests/qtest/npcm7xx_adc-test.c:267:16: error: declaration shadows a variable in the global scope [-Werror,-Wshadow] const ADC *adc = adc_p; ^ tests/qtest/npcm7xx_adc-test.c:293:16: error: declaration shadows a variable in the global scope [-Werror,-Wshadow] const ADC *adc = adc_p; ^ tests/qtest/npcm7xx_adc-test.c:311:16: error: declaration shadows a variable in the global scope [-Werror,-Wshadow] const ADC *adc = adc_p; ^ tests/qtest/npcm7xx_adc-test.c:93:5: note: previous declaration is here ADC adc = { ^ Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Message-ID: <20231009100251.56019-8-philmd@linaro.org> Signed-off-by: Thomas Huth <thuth@redhat.com>
2023-10-27tests/rtl8139: Clean up global variable shadowingPhilippe Mathieu-Daudé1-6/+6
Rename the variable to fix: tests/qtest/rtl8139-test.c:28:33: error: declaration shadows a variable in the global scope [-Werror,-Wshadow] static void save_fn(QPCIDevice *dev, int devfn, void *data) ^ tests/qtest/rtl8139-test.c:37:17: error: declaration shadows a variable in the global scope [-Werror,-Wshadow] QPCIDevice *dev; ^ tests/qtest/rtl8139-test.c:25:20: note: previous declaration is here static QPCIDevice *dev; ^ Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Message-ID: <20231009100251.56019-7-philmd@linaro.org> Signed-off-by: Thomas Huth <thuth@redhat.com>
2023-10-27tests/cdrom-test: Clean up global variable shadowing in prepare_image()Philippe Mathieu-Daudé1-3/+3
Rename the variable to fix: tests/qtest/cdrom-test.c:40:50: error: declaration shadows a variable in the global scope [-Werror,-Wshadow] static int prepare_image(const char *arch, char *isoimage) ^ tests/qtest/cdrom-test.c:18:13: note: previous declaration is here static char isoimage[] = "cdrom-boot-iso-XXXXXX"; ^ Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: John Snow <jsnow@redhat.com> Message-ID: <20231009100251.56019-5-philmd@linaro.org> Signed-off-by: Thomas Huth <thuth@redhat.com>
2023-10-27tests/virtio-scsi: Clean up global variable shadowingPhilippe Mathieu-Daudé1-1/+1
Rename the (unused) 'allow' argument, following the pattern used by the other tests in this file. This fixes: tests/qtest/virtio-scsi-test.c:159:61: error: declaration shadows a variable in the global scope [-Werror,-Wshadow] static void hotplug(void *obj, void *data, QGuestAllocator *alloc) ^ tests/qtest/virtio-scsi-test.c:37:25: note: previous declaration is here static QGuestAllocator *alloc; ^ Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-By: Emmanouil Pitsidianakis <manos.pitsidianakis@linaro.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Message-ID: <20231009100251.56019-4-philmd@linaro.org> Signed-off-by: Thomas Huth <thuth@redhat.com>
2023-10-20tests/qtest: Don't print messages from query instancesFabiano Rosas1-1/+8
Now that we can query more than one binary, the "starting QEMU..." message can get a little noisy. Mute those messages unless we're running with --verbose. Only affects qtest_init() calls from within libqtest. The tests continue to output as usual. Reviewed-by: Juan Quintela <quintela@redhat.com> Reviewed-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Fabiano Rosas <farosas@suse.de> Message-ID: <20231018192741.25885-13-farosas@suse.de> Signed-off-by: Juan Quintela <quintela@redhat.com>
2023-10-20tests/qtest/migration: Allow user to specify a machine typeFabiano Rosas3-2/+31
Accept the QTEST_QEMU_MACHINE_TYPE environment variable to take a machine type to use in the tests. The full machine type is recognized (e.g. pc-q35-8.2). Aliases (e.g. pc) are also allowed and resolve to the latest machine version for that alias, or, if using two QEMU binaries, to the latest common machine version between the two. Signed-off-by: Fabiano Rosas <farosas@suse.de> Reviewed-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Juan Quintela <quintela@redhat.com> Signed-off-by: Juan Quintela <quintela@redhat.com> Message-ID: <20231018192741.25885-12-farosas@suse.de>
2023-10-20tests/qtest/migration: Support more than one QEMU binaryFabiano Rosas1-4/+24
We have strict rules around migration compatibility between different QEMU versions but no test to validate the migration state between different binaries. Add infrastructure to allow running the migration tests with two different QEMU binaries as migration source and destination. The code now recognizes two new environment variables QTEST_QEMU_BINARY_SRC and QTEST_QEMU_BINARY_DST. In the absence of either of them, the test will use the QTEST_QEMU_BINARY variable. If both are missing then the tests are run with single binary as previously. The machine type is selected automatically as the latest machine type version that works with both binaries. Usage (only one of SRC|DST is allowed): QTEST_QEMU_BINARY_SRC=../build-8.2.0/qemu-system-x86_64 \ QTEST_QEMU_BINARY=../build-8.1.0/qemu-system-x86_64 \ ./tests/qtest/migration-test Reviewed-by: Juan Quintela <quintela@redhat.com> Signed-off-by: Fabiano Rosas <farosas@suse.de> Reviewed-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Juan Quintela <quintela@redhat.com> Message-ID: <20231018192741.25885-11-farosas@suse.de>
2023-10-20tests/qtest/migration: Set q35 as the default machine for x86_86Fabiano Rosas1-1/+6
Change the x86_64 to use the q35 machines in tests from now on. Keep testing the pc macine on 32bit. Signed-off-by: Fabiano Rosas <farosas@suse.de> Reviewed-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Juan Quintela <quintela@redhat.com> Signed-off-by: Juan Quintela <quintela@redhat.com> Message-ID: <20231018192741.25885-10-farosas@suse.de>
2023-10-20tests/qtest/migration: Specify the geometry of the bootsectorFabiano Rosas1-1/+3
We're about to enable the x86_64 tests to run with the q35 machine, but that machine does not work with the program we use to dirty the memory for the tests. The issue is that QEMU needs to guess the geometry of the "disk" we give to it and the guessed geometry doesn't pass the sanity checks done by SeaBIOS. This causes SeaBIOS to interpret the geometry as if needing a translation from LBA to CHS and SeaBIOS ends up miscomputing the number of cylinders and aborting due to that. The reason things work with the "pc" machine is that is uses ATA instead of AHCI like q35 and SeaBIOS has an exception for ATA that ends up skipping the sanity checks and ignoring translation altogether. Workaround this situation by specifying a geometry in the command line. Signed-off-by: Fabiano Rosas <farosas@suse.de> Acked-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Juan Quintela <quintela@redhat.com> Signed-off-by: Juan Quintela <quintela@redhat.com> Message-ID: <20231018192741.25885-9-farosas@suse.de>
2023-10-20tests/qtest/migration: Define a machine for all architecturesFabiano Rosas1-3/+13
Stop relying on defaults and select a machine explicitly for every architecture. This is a prerequisite for being able to select machine types for migration using different QEMU binaries for source and destination. Signed-off-by: Fabiano Rosas <farosas@suse.de> Reviewed-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Juan Quintela <quintela@redhat.com> Signed-off-by: Juan Quintela <quintela@redhat.com> Message-ID: <20231018192741.25885-8-farosas@suse.de>
2023-10-20tests/qtest/migration: Introduce find_common_machine_versionFabiano Rosas2-0/+28
When using two different QEMU binaries for migration testing, we'll need to find what is the machine version that will work with both binaries. Add a helper for that. Reviewed-by: Juan Quintela <quintela@redhat.com> Reviewed-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Fabiano Rosas <farosas@suse.de> Signed-off-by: Juan Quintela <quintela@redhat.com> Message-ID: <20231018192741.25885-7-farosas@suse.de>
2023-10-20tests/qtest: Introduce qtest_resolve_machine_aliasFabiano Rosas2-0/+26
The migration tests are being enhanced to test migration between different QEMU versions. A requirement of migration is that the machine type between source and destination matches, including the version. We cannot hardcode machine types in the tests because those change with each release. QEMU provides a machine type alias that has a fixed name, but points to the latest machine type at each release. Add a helper to resolve the alias into the exact machine type. E.g. "-machine pc" resolves to "pc-i440fx-8.2" Reviewed-by: Juan Quintela <quintela@redhat.com> Reviewed-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Fabiano Rosas <farosas@suse.de> Signed-off-by: Juan Quintela <quintela@redhat.com> Message-ID: <20231018192741.25885-6-farosas@suse.de>
2023-10-20tests/qtest: Introduce qtest_has_machine_with_envFabiano Rosas2-2/+16
Add a variant of qtest_has_machine() that receives an environment variable containing an alternate QEMU binary path. Reviewed-by: Juan Quintela <quintela@redhat.com> Reviewed-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Fabiano Rosas <farosas@suse.de> Signed-off-by: Juan Quintela <quintela@redhat.com> Message-ID: <20231018192741.25885-5-farosas@suse.de>
2023-10-20tests/qtest: Allow qtest_get_machines to use an alternate QEMU binaryFabiano Rosas1-4/+25
We're adding support for using more than one QEMU binary in tests. Modify qtest_get_machines() to take an environment variable that contains the QEMU binary path. Since the function keeps a cache of the machines list in the form of a static variable, refresh it any time the environment variable changes. Reviewed-by: Juan Quintela <quintela@redhat.com> Reviewed-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Fabiano Rosas <farosas@suse.de> Signed-off-by: Juan Quintela <quintela@redhat.com> Message-ID: <20231018192741.25885-4-farosas@suse.de>
2023-10-20tests/qtest: Introduce qtest_init_with_envFabiano Rosas2-7/+32
Add a version of qtest_init() that takes an environment variable containing the path of the QEMU binary. This allows tests to use more than one QEMU binary. If no variable is provided or the environment variable does not exist, that is not an error. Fallback to using QTEST_QEMU_BINARY. Signed-off-by: Fabiano Rosas <farosas@suse.de> Reviewed-by: Juan Quintela <quintela@redhat.com> Reviewed-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Juan Quintela <quintela@redhat.com> Message-ID: <20231018192741.25885-3-farosas@suse.de>
2023-10-20tests/qtest: Allow qtest_qemu_binary to use a custom environment variableFabiano Rosas1-3/+10
We're adding support for testing migration using two different QEMU binaries. We'll provide the second binary in a new environment variable. Allow qtest_qemu_binary() to receive the name of the new variable. If the new environment variable is not set, that's not an error, we use QTEST_QEMU_BINARY as a fallback. Reviewed-by: Juan Quintela <quintela@redhat.com> Reviewed-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Fabiano Rosas <farosas@suse.de> Signed-off-by: Juan Quintela <quintela@redhat.com> Message-ID: <20231018192741.25885-2-farosas@suse.de>
2023-10-20tests/qtest/migration-test: Disable the analyze-migration.py test on s390xThomas Huth1-1/+3
The analyze-migration.py script fails on s390x hosts: Traceback (most recent call last): File "scripts/analyze-migration.py", line 662, in <module> dump.read(dump_memory = args.memory) File "scripts/analyze-migration.py", line 596, in read classdesc = self.section_classes[section_key] KeyError: ('s390-storage_attributes', 0) It obviously never has been adapted to s390x yet, so until this has been done, disable this test on s390x. Signed-off-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Juan Quintela <quintela@redhat.com> Signed-off-by: Juan Quintela <quintela@redhat.com> Message-ID: <20231018091239.164452-1-thuth@redhat.com>
2023-10-17tests/qtest: migration-test: Add tests for file-based migrationFabiano Rosas1-0/+147
Add basic tests for file-based migration. Note that we cannot use test_precopy_common because that routine expects it to be possible to run the migration live. With the file transport there is no live migration because we must wait for the source to finish writing the migration data to the file before the destination can start reading. Add a new migration function specifically to handle the file migration. Reviewed-by: Peter Xu <peterx@redhat.com> Reviewed-by: Juan Quintela <quintela@redhat.com> Signed-off-by: Fabiano Rosas <farosas@suse.de> Signed-off-by: Juan Quintela <quintela@redhat.com> Message-ID: <20230712190742.22294-7-farosas@suse.de>
2023-10-17tests/qtest/migration: Add a test for the analyze-migration scriptFabiano Rosas2-0/+62
Add a smoke test that migrates to a file and gives it to the script. It should catch the most annoying errors such as changes in the ram flags. After code has been merged it becomes way harder to figure out what is causing the script to fail, the person making the change is the most likely to know right away what the problem is. Signed-off-by: Fabiano Rosas <farosas@suse.de> Acked-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Juan Quintela <quintela@redhat.com> Signed-off-by: Juan Quintela <quintela@redhat.com> Message-ID: <20231009184326.15777-7-farosas@suse.de>
2023-10-16Merge tag 'pull-ufs-20231013' of https://gitlab.com/jeuk20.kim/qemu into stagingStefan Hajnoczi1-1/+1
hw/ufs: fixes # -----BEGIN PGP SIGNATURE----- # # iQIzBAABCgAdFiEEUBfYMVl8eKPZB+73EuIgTA5dtgIFAmUozswACgkQEuIgTA5d # tgITExAAo0BSNir4I5MfeNIjZTNNdxLXDl0+92JyairB2m/gWH/02jGtrJBYp5On # ELnixKj2Ntn9IIRr3NwQHNTnDOZHRkUBH+pRVeMbZ+IWLjEoWQdl03ge7e9sHai3 # CLXB4HPSnXddy1SmS9FEkdBWopqxKF4BLZnpAfwh/dj2fzSyDyNIMmGoRimRQhph # 9A90304ERUdpREAXncTgSdXeDZz+lScadzUJZrPPiG2ZHXL+qzDCX7ojEnNaUFxz # W1IfriI8oeeORfCQaNEOncLKhSwE1WscGxP0vILPApKOu251tObgSbK90QlQR2qT # BMl7k4BDfYeksXMGc0BXVFrOfv1ud86NlCE2OokK6HBZVuHio4C6TU/t65MC4Rw5 # mJ8CPgbN+7sgVmAGo0sLYzI6GiRR27VqqLh6KXVAa5c/fAdt5pHSkakwSvxiXsAl # EqskmOY2em5O//+7CWN1CtY+I2pHyltMXAi3Cb2vjweNx88kuhmxFQWeZVI10/H3 # gNrNfu32+ihDLMqR7uQamdAZV0lnIwp97nCbf3LzpM0btjl70QvGZhsbiCDiLQrG # mJjnaix4xDb8T21WKrI8DKcwR4rvD8hZsCUp31XJnA8HWtdPnEQldK8NEGNlU5ye # lrGc6gxiwZLCBBIj9lwbZW3Zv9Vz9jNWISOmY+KWLCIus98DBxQ= # =XXsQ # -----END PGP SIGNATURE----- # gpg: Signature made Fri 13 Oct 2023 00:59:56 EDT # gpg: using RSA key 5017D831597C78A3D907EEF712E2204C0E5DB602 # gpg: Good signature from "Jeuk Kim <jeuk20.kim@samsung.com>" [unknown] # gpg: aka "Jeuk Kim <jeuk20.kim@gmail.com>" [unknown] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 5017 D831 597C 78A3 D907 EEF7 12E2 204C 0E5D B602 * tag 'pull-ufs-20231013' of https://gitlab.com/jeuk20.kim/qemu: hw/ufs: Fix incorrect register fields hw/ufs: Fix code coverity issues Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2023-10-13hw/ufs: Fix code coverity issuesJeuk Kim1-1/+1
Fixed four ufs-related coverity issues. The coverity issues and fixes are as follows 1. CID 1519042: Security issue with the rand() function Changed to use a fixed value (0xab) instead of rand() as the value for testing 2. CID 1519043: Dereference after null check Removed useless (redundant) null checks 3. CID 1519050: Out-of-bounds access issue Fix to pass an array type variable to find_first_bit and find_next_bit using DECLARE_BITMAP() 4. CID 1519051: Out-of-bounds read issue Fix incorrect range check for lun Fix coverity CID: 1519042 1519043 1519050 1519051 Signed-off-by: Jeuk Kim <jeuk20.kim@samsung.com>
2023-10-12tests/qtest: Fix npcm7xx_timer-test.c flaky testChris Rauer1-0/+1
npcm7xx_timer-test occasionally fails due to the state of the timers from the previous test iteration. Advancing the clock step after the reset resolves this issue. Fixes: https://gitlab.com/qemu-project/qemu/-/issues/1897 Signed-off-by: Chris Rauer <crauer@google.com> Message-ID: <20230929000831.691559-1-crauer@google.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
2023-10-11tests/qtest: migration: Add support for negative testing of qmp_migrateFabiano Rosas5-4/+96
There is currently no way to write a test for errors that happened in qmp_migrate before the migration has started. Add a version of qmp_migrate that ensures an error happens. To make use of it a test needs to set MigrateCommon.result as MIG_TEST_QMP_ERROR. Reviewed-by: Peter Xu <peterx@redhat.com> Reviewed-by: Juan Quintela <quintela@redhat.com> Signed-off-by: Fabiano Rosas <farosas@suse.de> Signed-off-by: Juan Quintela <quintela@redhat.com> Message-ID: <20230712190742.22294-6-farosas@suse.de>
2023-10-11tests/qtest: migration: Use migrate_incoming_qmp where appropriateFabiano Rosas3-76/+14
Use the new migrate_incoming_qmp helper in the places that currently open-code calling migrate-incoming. Reviewed-by: Juan Quintela <quintela@redhat.com> Reviewed-by: Peter Xu <peterx@redhat.com> Signed-off-by: Fabiano Rosas <farosas@suse.de> Signed-off-by: Juan Quintela <quintela@redhat.com> Message-ID: <20230712190742.22294-4-farosas@suse.de>
2023-10-11tests/qtest: migration: Add migrate_incoming_qmp helperFabiano Rosas2-0/+33
file-based migration requires the target to initiate its migration after the source has finished writing out the data in the file. Currently there's no easy way to initiate 'migrate-incoming', allow this by introducing migrate_incoming_qmp helper, similarly to migrate_qmp. Also make sure migration events are enabled and wait for the incoming migration to start before returning. This avoid a race when querying the migration status too soon after issuing the command. Reviewed-by: Peter Xu <peterx@redhat.com> Reviewed-by: Juan Quintela <quintela@redhat.com> Signed-off-by: Fabiano Rosas <farosas@suse.de> Signed-off-by: Juan Quintela <quintela@redhat.com> Message-ID: <20230712190742.22294-3-farosas@suse.de>
2023-10-11tests/qtest: migration: Expose migrate_set_capabilityFabiano Rosas3-11/+14
The following patch will make use of this function from within migrate-helpers.c, so move it there. Reviewed-by: Juan Quintela <quintela@redhat.com> Reviewed-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Peter Xu <peterx@redhat.com> Signed-off-by: Fabiano Rosas <farosas@suse.de> Signed-off-by: Juan Quintela <quintela@redhat.com> Message-ID: <20230712190742.22294-2-farosas@suse.de>
2023-10-10Merge tag 'firmware/seabios-20231010-pull-request' of ↵Stefan Hajnoczi1-0/+2
https://gitlab.com/kraxel/qemu into staging seabios: update to git snapshot Give seabios a bit real world testing before tagging a release. Update to release will follow later in the devel cycle. v3: update mmio64 acpi test. # -----BEGIN PGP SIGNATURE----- # # iQIzBAABCgAdFiEEoDKM/7k6F6eZAf59TLbY7tPocTgFAmUlNMUACgkQTLbY7tPo # cTgp5RAA154WTGRGEoBveu8ocIVNzPxDB8esLBDmsQ7VSKo6e7wJvS+IyPBVYDSW # O0p8Hr/2WlXV1BA1pVUyxzEN4AwqiRDBw4Elir6n//MF7r0wR84401hz6er+4O8j # U/xkMXPL/mVV+dulNq+ACjt0nRWIQgdlxEnIl9AY7Nbx3l8NM70PrxRbiG/CtRUz # gJW3uDU5xRWWGsI7tO8ZEuB2RRQ9B1uCw2ljx9QbxDonJABLUe6YVOI/QhBboX4B # 2lIezGxRzDwvCdgHXCraakm0ZE6fL9FlHJ4tyapWt21ggkHA6+5oPcx/zisNuCIy # EMiu6p7ttlC3AiaXUmjdCYboRzNKV+S6NvweqzQis5aUedomuFDt3yKo8BqHdzkO # uxSFbzpVxXzSXer1OlRZfVGxME35oyfPfeRPVNpef4zg/XdtOeAhckMVHr72QqEd # pRyR2x+CTxzJ2SsbQ21AS+0PUtEa3JHcna6VMlblCO4uRppb/cnpq6SA2m343PCB # D9IVgtui7+VEbaTxMmkUfOLTP/+QQnF6KOCcOlGtB6HjzqNfJnwuu2k6RsYCkdZf # 3tJIdVv72LsopZNHYrqm7iU3XpEBGqFdv3Dq3pm35uW1nRKBdr2VQPjANfttHKxd # pUFve1EObHDRTbEFXI0ALvdlDLSX/54McTFF9BKuRPyuxJKyvPM= # =7FXs # -----END PGP SIGNATURE----- # gpg: Signature made Tue 10 Oct 2023 07:25:57 EDT # gpg: using RSA key A0328CFFB93A17A79901FE7D4CB6D8EED3E87138 # gpg: Good signature from "Gerd Hoffmann (work) <kraxel@redhat.com>" [full] # gpg: aka "Gerd Hoffmann <gerd@kraxel.org>" [full] # gpg: aka "Gerd Hoffmann (private) <kraxel@gmail.com>" [full] # Primary key fingerprint: A032 8CFF B93A 17A7 9901 FE7D 4CB6 D8EE D3E8 7138 * tag 'firmware/seabios-20231010-pull-request' of https://gitlab.com/kraxel/qemu: tests/acpi: disable tests/data/acpi/q35/DSDT.mmio64 updates tests/acpi: update expected data files seabios: update binaries to git snapshot seabios: update submodule to git snapshot tests/acpi: enable tests/data/acpi/q35/DSDT.mmio64 updates tests/bios-tables-test: tcg-emulate opteron for mmio64 test Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2023-10-10tests/acpi: disable tests/data/acpi/q35/DSDT.mmio64 updatesGerd Hoffmann1-1/+0
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
2023-10-10tests/acpi: enable tests/data/acpi/q35/DSDT.mmio64 updatesGerd Hoffmann1-0/+1
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
2023-10-10tests/bios-tables-test: tcg-emulate opteron for mmio64 testGerd Hoffmann1-0/+2
seabios starts to make the placement of the 64bit mmio window depend on the physical address space. Run the testcase with a fixed processor on tcg to avoid different results depending on the host machine. Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
2023-10-08audio, qtest: get rid of QEMU_AUDIO_DRVPaolo Bonzini1-3/+1
Default audio devices can now be created with "-audio". Tests for soundcards were already using "-audiodev" if they want to specify a particular backend, for the others remove the last remnants of legacy audio configuration. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2023-10-07fuzz: Correct invalid mentions of 'softmmu' by 'system'Philippe Mathieu-Daudé2-3/+3
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Alexander Bulekov <alxndr@bu.edu> Message-ID: <20231004090629.37473-5-philmd@linaro.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2023-10-05Merge tag 'for_upstream' of https://git.kernel.org/pub/scm/virt/kvm/mst/qemu ↵Stefan Hajnoczi2-9/+24
into staging virtio,pci: features, cleanups vdpa: shadow vq vlan support net migration with cvq cxl: support emulating 4 HDM decoders serial number extended capability virtio: hared dma-buf Fixes, cleanups all over the place. Signed-off-by: Michael S. Tsirkin <mst@redhat.com> * tag 'for_upstream' of https://git.kernel.org/pub/scm/virt/kvm/mst/qemu: (53 commits) libvhost-user: handle shared_object msg vhost-user: add shared_object msg hw/display: introduce virtio-dmabuf util/uuid: add a hash function virtio: remove unused next argument from virtqueue_split_read_next_desc() virtio: remove unnecessary thread fence while reading next descriptor virtio: use shadow_avail_idx while checking number of heads libvhost-user.c: add assertion to vu_message_read_default pcie_sriov: unregister_vfs(): fix error path hw/i386/pc: improve physical address space bound check for 32-bit x86 systems amd_iommu: Fix APIC address check vdpa net: follow VirtIO initialization properly at cvq isolation probing vdpa net: stop probing if cannot set features vdpa net: fix error message setting virtio status hw/pci-bridge/cxl-upstream: Add serial number extended capability support hw/cxl: Support 4 HDM decoders at all levels of topology hw/cxl: Fix and use same calculation for HDM decoder block size everywhere hw/cxl: Add utility functions decoder interleave ways and target count. hw/cxl: Push cxl_decoder_count_enc() and cxl_decode_ig() into .c vdpa net: zero vhost_vdpa iova_tree pointer at cleanup ... Conflicts: hw/core/machine.c Context conflict with commit 314e0a84cd5d ("hw/core: remove needless includes") because it removed an adjacent #include.
2023-10-04hw/i386/pc: improve physical address space bound check for 32-bit x86 systemsAni Sinha2-9/+24
32-bit x86 systems do not have a reserved memory for hole64. On those 32-bit systems without PSE36 or PAE CPU features, hotplugging memory devices are not supported by QEMU as QEMU always places hotplugged memory above 4 GiB boundary which is beyond the physical address space of the processor. Linux guests also does not support memory hotplug on those systems. Please see Linux kernel commit b59d02ed08690 ("mm/memory_hotplug: disable the functionality for 32b") for more details. Therefore, the maximum limit of the guest physical address in the absence of additional memory devices effectively coincides with the end of "above 4G memory space" region for 32-bit x86 without PAE/PSE36. When users configure additional memory devices, after properly accounting for the additional device memory region to find the maximum value of the guest physical address, the address will be outside the range of the processor's physical address space. This change adds improvements to take above into consideration. For example, previously this was allowed: $ ./qemu-system-x86_64 -cpu pentium -m size=10G With this change now it is no longer allowed: $ ./qemu-system-x86_64 -cpu pentium -m size=10G qemu-system-x86_64: Address space limit 0xffffffff < 0x2bfffffff phys-bits too low (32) However, the following are allowed since on both cases physical address space of the processor is 36 bits: $ ./qemu-system-x86_64 -cpu pentium2 -m size=10G $ ./qemu-system-x86_64 -cpu pentium,pse36=on -m size=10G For 32-bit, without PAE/PSE36, hotplugging additional memory is no longer allowed. $ ./qemu-system-i386 -m size=1G,maxmem=3G,slots=2 qemu-system-i386: Address space limit 0xffffffff < 0x1ffffffff phys-bits too low (32) $ ./qemu-system-i386 -machine q35 -m size=1G,maxmem=3G,slots=2 qemu-system-i386: Address space limit 0xffffffff < 0x1ffffffff phys-bits too low (32) A new compatibility flag is introduced to make sure pc_max_used_gpa() keeps returning the old value for machines 8.1 and older. Therefore, the above is still allowed for older machine types in order to support compatibility. Hence, the following still works: $ ./qemu-system-i386 -machine pc-i440fx-8.1 -m size=1G,maxmem=3G,slots=2 $ ./qemu-system-i386 -machine pc-q35-8.1 -m size=1G,maxmem=3G,slots=2 Further, following is also allowed as with PSE36, the processor has 36-bit address space: $ ./qemu-system-i386 -cpu 486,pse36=on -m size=1G,maxmem=3G,slots=2 After calling CPUID with EAX=0x80000001, all AMD64 compliant processors have the longmode-capable-bit turned on in the extended feature flags (bit 29) in EDX. The absence of CPUID longmode can be used to differentiate between 32-bit and 64-bit processors and is the recommended approach. QEMU takes this approach elsewhere (for example, please see x86_cpu_realizefn()), With this change, pc_max_used_gpa() also uses the same method to detect 32-bit processors. Unit tests are modified to not run 32-bit x86 tests that use memory hotplug. Suggested-by: David Hildenbrand <david@redhat.com> Signed-off-by: Ani Sinha <anisinha@redhat.com> Reviewed-by: David Hildenbrand <david@redhat.com> Message-Id: <20230922160413.165702-1-anisinha@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2023-09-29migration-test: simplify shmem_opts handlingJuan Quintela1-5/+2
Reviewed-by: Peter Xu <peterx@redhat.com> Message-ID: <20230608224943.3877-4-quintela@redhat.com> Signed-off-by: Juan Quintela <quintela@redhat.com>
generated by cgit v1.1 at 2025-09-25 16:23:23 +0000