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2024-03-05tests/qtest/stm32l4x5_rcc-test.c: Add tests for the STM32L4x5_RCCArnaud Minier2-1/+191
Tests: - the ability to change the sysclk of the device - the ability to enable/disable/configure the PLLs - if the clock multiplexers work - the register flags and the generation of irqs Signed-off-by: Arnaud Minier <arnaud.minier@telecom-paris.fr> Signed-off-by: Inès Varhol <ines.varhol@telecom-paris.fr> Acked-by: Thomas Huth <thuth@redhat.com> Message-id: 20240303140643.81957-9-arnaud.minier@telecom-paris.fr Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
2024-03-05tests/qtest: Add testcase for BCM2835 BSCRayhan Faizel2-1/+116
Simple testcase for validating proper operation of read and write for all three BSC controllers. Signed-off-by: Rayhan Faizel <rayhan.faizel@gmail.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20240224191038.2409945-4-rayhan.faizel@gmail.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-03-05Merge tag 'migration-next-pull-request' of https://gitlab.com/peterx/qemu ↵Peter Maydell1-0/+137
into staging Migartion pull request for 20240304 - Bryan's fix on multifd compression level API - Fabiano's mapped-ram series (base + multifd only) - Steve's amend on cpr document in qapi/ # -----BEGIN PGP SIGNATURE----- # # iIgEABYKADAWIQS5GE3CDMRX2s990ak7X8zN86vXBgUCZeUjKhIccGV0ZXJ4QHJl # ZGhhdC5jb20ACgkQO1/MzfOr1wbv5QD/ZexBUsmZA5qyxgGvZ2yvlUBEGNOvtmKY # kRdiYPU7khMA/0N43rn4LcqKCoq4+T+EAnYizGjIyhH/7BRUyn4DUxgO # =AeEn # -----END PGP SIGNATURE----- # gpg: Signature made Mon 04 Mar 2024 01:26:02 GMT # gpg: using EDDSA key B9184DC20CC457DACF7DD1A93B5FCCCDF3ABD706 # gpg: issuer "peterx@redhat.com" # gpg: Good signature from "Peter Xu <xzpeter@gmail.com>" [marginal] # gpg: aka "Peter Xu <peterx@redhat.com>" [marginal] # gpg: WARNING: This key is not certified with sufficiently trusted signatures! # gpg: It is not certain that the signature belongs to the owner. # Primary key fingerprint: B918 4DC2 0CC4 57DA CF7D D1A9 3B5F CCCD F3AB D706 * tag 'migration-next-pull-request' of https://gitlab.com/peterx/qemu: (27 commits) migration/multifd: Document two places for mapped-ram tests/qtest/migration: Add a multifd + mapped-ram migration test migration/multifd: Add mapped-ram support to fd: URI migration/multifd: Support incoming mapped-ram stream format migration/multifd: Support outgoing mapped-ram stream format migration/multifd: Prepare multifd sync for mapped-ram migration migration/multifd: Add incoming QIOChannelFile support migration/multifd: Add outgoing QIOChannelFile support migration/multifd: Add a wrapper for channels_created migration/multifd: Allow receiving pages without packets migration/multifd: Allow multifd without packets migration/multifd: Decouple recv method from pages migration/multifd: Rename MultiFDSend|RecvParams::data to compress_data tests/qtest/migration: Add tests for mapped-ram file-based migration migration/ram: Add incoming 'mapped-ram' migration migration/ram: Add outgoing 'mapped-ram' migration migration: Add mapped-ram URI compatibility check migration/ram: Introduce 'mapped-ram' migration capability migration/qemu-file: add utility methods for working with seekable channels io: fsync before closing a file channel ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org> # Conflicts: # migration/ram.c
2024-03-01tests/qtest/migration: Add a multifd + mapped-ram migration testFabiano Rosas1-0/+68
Reviewed-by: Peter Xu <peterx@redhat.com> Signed-off-by: Fabiano Rosas <farosas@suse.de> Link: https://lore.kernel.org/r/20240229153017.2221-24-farosas@suse.de Signed-off-by: Peter Xu <peterx@redhat.com>
2024-03-01tests/qtest/migration: Add tests for mapped-ram file-based migrationFabiano Rosas1-0/+59
Reviewed-by: Peter Xu <peterx@redhat.com> Signed-off-by: Fabiano Rosas <farosas@suse.de> Link: https://lore.kernel.org/r/20240229153017.2221-12-farosas@suse.de Signed-off-by: Peter Xu <peterx@redhat.com>
2024-03-01libqos/virtio.c: fix 'avail_event' offset in qvring_init()Daniel Henrique Barboza1-1/+1
In qvring_init() we're writing vq->used->avail_event at "vq->used + 2 + array_size". The struct pointed by vq->used is, from virtio_ring.h Linux header): * // A ring of used descriptor heads with free-running index. * __virtio16 used_flags; * __virtio16 used_idx; * struct vring_used_elem used[num]; * __virtio16 avail_event_idx; So 'flags' is the word right at vq->used. 'idx' is vq->used + 2. We need to skip 'used_idx' by adding + 2 bytes, and then sum the vector size, to reach avail_event_idx. An example on how to properly access this field can be found in qvirtqueue_kick(): avail_event = qvirtio_readw(d, qts, vq->used + 4 + sizeof(struct vring_used_elem) * vq->size); This error was detected when enabling the RISC-V 'virt' libqos machine. The 'idx' test from vhost-user-blk-test.c errors out with a timeout in qvirtio_wait_used_elem(). The timeout happens because when processing the first element, 'avail_event' is read in qvirtqueue_kick() as non-zero because we didn't initialize it properly (and the memory at that point happened to be non-zero). 'idx' is 0. All of this makes this condition fail because "idx - avail_event" will overflow and be non-zero: /* < 1 because we add elements to avail queue one by one */ if ((flags & VRING_USED_F_NO_NOTIFY) == 0 && (!vq->event || (uint16_t)(idx-avail_event) < 1)) { d->bus->virtqueue_kick(d, vq); } As a result the virtqueue is never kicked and we'll timeout waiting for it. Fixes: 1053587c3f ("libqos: Added EVENT_IDX support") Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Thomas Huth <thuth@redhat.com> Message-ID: <20240217192607.32565-3-dbarboza@ventanamicro.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
2024-03-01libqos/virtio.c: init all elems in qvring_indirect_desc_setup()Daniel Henrique Barboza1-6/+19
The loop isn't setting the values for the last element. Every other element is being initialized with addr = 0, flags = VRING_DESC_F_NEXT and next = i + 1. The last elem is never touched. This became a problem when enabling a RISC-V 'virt' libqos machine in the 'indirect' test of virti-blk-test.c. The 'flags' for the last element will end up being an odd number (since we didn't touch it). Being an odd number it will be mistaken by VRING_DESC_F_NEXT, which happens to be 1. Deep into hw/virt/virtio.c, in virtqueue_split_pop(), into virtqueue_split_read_next_desc(), a check for VRING_DESC_F_NEXT will be made to see if we're supposed to chain. The code will keep up chaining in the last element because the uninitialized value happens to be odd. We'll error out right after that because desc->next (which is also uninitialized) will be >= max. A VIRTQUEUE_READ_DESC_ERROR will be returned, with an error message like this in the stderr: qemu-system-riscv64: Desc next is 49391 Since we never returned, we'll end up timing out at qvirtio_wait_used_elem(): ERROR:../tests/qtest/libqos/virtio.c:236:qvirtio_wait_used_elem: assertion failed: (g_get_monotonic_time() - start_time <= timeout_us) The root cause is using uninitialized values from guest_alloc() in qvring_indirect_desc_setup(). There's no guarantee that the memory pages retrieved will be zeroed, so we can't make assumptions. In fact, commit 5b4f72f5e8 ("tests/qtest: properly initialise the vring used idx") fixed a similar problem stating "It is probably not wise to assume guest memory is zeroed anyway". I concur. Initialize all elems in qvring_indirect_desc_setup(). Fixes: f294b029aa ("libqos: Added indirect descriptor support to virtio implementation") Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Thomas Huth <thuth@redhat.com> Message-ID: <20240217192607.32565-2-dbarboza@ventanamicro.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
2024-03-01tests/migration: Set compression level in migration testsBryan Zhang1-0/+10
Adds calls to set compression level for `zstd` and `zlib` migration tests, just to make sure that the calls work. Signed-off-by: Bryan Zhang <bryan.zhang@bytedance.com> Link: https://lore.kernel.org/r/20240301035901.4006936-3-bryan.zhang@bytedance.com Signed-off-by: Peter Xu <peterx@redhat.com>
2024-02-28tests/qtest/migration: Add a fd + file testFabiano Rosas1-0/+41
The fd URI supports an fd that is backed by a file. The code should select between QIOChannelFile and QIOChannelSocket, depending on the type of the fd. Add a test for that. Signed-off-by: Fabiano Rosas <farosas@suse.de> Reviewed-by: Peter Xu <peterx@redhat.com> Link: https://lore.kernel.org/r/20240220224138.24759-4-farosas@suse.de Signed-off-by: Peter Xu <peterx@redhat.com>
2024-02-28tests/qtest/migration: Rename fd_proto testFabiano Rosas1-2/+3
Next patch adds another fd test. Rename the existing one closer to what's used on other tests, with the 'precopy' prefix. Signed-off-by: Fabiano Rosas <farosas@suse.de> Reviewed-by: Peter Xu <peterx@redhat.com> Link: https://lore.kernel.org/r/20240220224138.24759-3-farosas@suse.de Signed-off-by: Peter Xu <peterx@redhat.com>
2024-02-27tests/qtest: Check that EXTI fan-in irqs are correctly connectedInès Varhol1-0/+37
This commit adds a QTest that verifies each input line of a specific EXTI OR gate can influence the output line. Signed-off-by: Inès Varhol <ines.varhol@telecom-paris.fr> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20240220184145.106107-3-ines.varhol@telecom-paris.fr Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-02-24Merge tag 'pull-request-2024-02-23' of https://gitlab.com/thuth/qemu into ↵Peter Maydell3-3/+20
staging * m68k: Fix exception frame format for 68010 * Add cdrom test for LoongArch virt machine * Fix qtests when using --without-default-devices * Enable -Wvla * Windows 32-bit removal * Silence warnings in the test-x86-cpuid-compat qtest # -----BEGIN PGP SIGNATURE----- # # iQJFBAABCAAvFiEEJ7iIR+7gJQEY8+q5LtnXdP5wLbUFAmXY7MMRHHRodXRoQHJl # ZGhhdC5jb20ACgkQLtnXdP5wLbWkRg//TCprQ7Gesex/yvMFIZuZk+poEaibxGXU # cWp6hneV8selTzBKzBC3VS1n31shd9astNRE95N2fSIfCV6R22y2tfZF2rSOoeog # bvqX7KoaEnSsrDS054EGAnuvYQpOGLGth/3Mc9Z791r5I1tYZPJocVnAyi/OB+3q # Gr5WzXj6Z/QD7c0f6vZ943wRBO/zc1729KikDUSyfS3Tua+15mAuUIUQdlLNNPct # 6aT5e6c967mAYh93AUevd3hgVYXH2W4fH7s1q2pap2hMBw2a43XvlMKJ9CvXPFPg # eU6knRPES16BSC2TTphNCBQi9n3rQdion01VsoQEetVBfFa4yA1Ys7ofF5vCa2l8 # 5EO5X3VQfZeq0ktmrLM7qAO0OMnolIqbeNS97ggOiyL0Q3YXim6cNWf8+OZbGoFR # OK88ndmzEXrZq+5w4QBDGLHFU3u8ZeWAM6p7Ht/ZN89ndDYT5bGBwkjVRW5hVgck # fmGhgutSqP2/DN5/4nMn8jtmGc65H/rBRilttW8W2JF72rQJYduDnx/A4KUatkHT # tC58NwLarF3kF7cebhWvNQDD74ia/35n+fEAmtIHF42YHE6aifss91QrgT+qGG5+ # GG12JIoFVDCgE1pkNU7GO53Uqo94Ej8TUOxwF9QfftxnqiktMG7Y/KQRcSA5VvHr # laagGgDzHP0= # =1hu9 # -----END PGP SIGNATURE----- # gpg: Signature made Fri 23 Feb 2024 19:06:43 GMT # gpg: using RSA key 27B88847EEE0250118F3EAB92ED9D774FE702DB5 # gpg: issuer "thuth@redhat.com" # gpg: Good signature from "Thomas Huth <th.huth@gmx.de>" [full] # gpg: aka "Thomas Huth <thuth@redhat.com>" [full] # gpg: aka "Thomas Huth <huth@tuxfamily.org>" [full] # gpg: aka "Thomas Huth <th.huth@posteo.de>" [unknown] # Primary key fingerprint: 27B8 8847 EEE0 2501 18F3 EAB9 2ED9 D774 FE70 2DB5 * tag 'pull-request-2024-02-23' of https://gitlab.com/thuth/qemu: target/i386: do not filter processor tracing features except on KVM .gitlab-ci.d/windows.yml: Remove shared-msys2 abstraction .gitlab-ci.d: Drop cross-win32-system job docs: Document that 32-bit Windows is unsupported meson: Enable -Wvla target/ppc/kvm: Replace variable length array in kvmppc_read_hptes() target/ppc/kvm: Replace variable length array in kvmppc_save_htab() tests: skip dbus-display tests that need a console tests/qtest: Fix boot-serial-test when using --without-default-devices tests/cdrom-test: Add cdrom test for LoongArch virt machine target/m68k: Fix exception frame format for 68010 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-02-23ppc/pnv: Test pnv i2c master and connected devicesGlenn Miles4-60/+573
Tests the following for both P9 and P10: - I2C master POR status - I2C master status after immediate reset Tests the following for powernv10-ranier only: - Config pca9552 hotplug device pins as inputs then Read the INPUT0/1 registers to verify all pins are high - Connected GPIO pin tests of P10 PCA9552 device. Tests output of pins 0-4 affect input of pins 5-9 respectively. - PCA9554 GPIO pins test. Tests input and ouput functionality. Reviewed-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Glenn Miles <milesg@linux.vnet.ibm.com> Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
2024-02-23misc/pca9552: Fix inverted input statusGlenn Miles1-3/+3
The pca9552 INPUT0 and INPUT1 registers are supposed to hold the logical values of the LED pins. A logical 0 should be seen in the INPUT0/1 registers for a pin when its corresponding LSn bits are set to 0, which is also the state needed for turning on an LED in a typical usage scenario. Existing code was doing the opposite and setting INPUT0/1 bit to a 1 when the LSn bit was set to 0, so this commit fixes that. Reviewed-by: Andrew Jeffery <andrew@codeconstruct.com.au> Signed-off-by: Glenn Miles <milesg@linux.vnet.ibm.com> Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
2024-02-23tests: skip dbus-display tests that need a consoleMarc-André Lureau1-2/+14
When compiling with "configure --without-default-devices", the dbus-display-test fails since it implicitly assumes that the machine comes with a default console. There doesn't seem to be an easy way to figure this during build time, so skip the tests requiring the Console interface at runtime. Reported-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com> Message-ID: <20240221073759.171443-1-marcandre.lureau@redhat.com> Tested-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
2024-02-23tests/qtest: Fix boot-serial-test when using --without-default-devicesThomas Huth1-1/+1
If "configure" has been run with "--without-default-devices", there is no e1000 device in the binaries, so the boot-serial-test currently fails in that case since it tries to use the e1000 with the sam460ex machine. Since we're testing the serial output here, and not the NIC, let's simply switch to the "pci-bridge" device here instead, which should always be there for PCI-based machines like the sam460ex. Message-ID: <20240219111030.384158-1-thuth@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
2024-02-23tests/cdrom-test: Add cdrom test for LoongArch virt machineBibo Mao1-0/+5
The cdrom test skips to execute on LoongArch system with command "make check", this patch enables cdrom test for LoongArch virt machine platform. With this patch, cdrom test passes to run on LoongArch virt machine type. Signed-off-by: Bibo Mao <maobibo@loongson.cn> Message-ID: <20240217100230.134042-1-maobibo@loongson.cn> Reviewed-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
2024-02-16tests/qtest: Depend on dbus_display1_depAkihiko Odaki1-1/+1
It ensures dbus-display1.c will not be recompiled. Signed-off-by: Akihiko Odaki <akihiko.odaki@daynix.com> Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com> Message-Id: <20240214-dbus-v7-3-7eff29f04c34@daynix.com>
2024-02-15tests/qtest: Fix GMAC test to run on a machine in upstream QEMUNabih Estefan2-83/+4
Fix the nocm_gmac-test.c file to run on a nuvoton 7xx machine instead of 8xx. Also fix comments referencing this and values expecting 8xx. Change-Id: Iabd0fba14910c3f1e883c4a9521350f3db9ffab8 Signed-Off-By: Nabih Estefan <nabihestefan@google.com> Reviewed-by: Tyrone Ting <kfting@nuvoton.com> Message-id: 20240208194759.2858582-2-nabihestefan@google.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> [PMM: commit message tweaks] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-02-15tests/qtest/npcm7xx_emc-test: Connect all NICs to a backendPeter Maydell1-1/+4
Currently QEMU will warn if there is a NIC on the board that is not connected to a backend. By default the '-nic user' will get used for all NICs, but if you manually connect a specific NIC to a specific backend, then the other NICs on the board have no backend and will be warned about: qemu-system-arm: warning: nic npcm7xx-emc.1 has no peer qemu-system-arm: warning: nic npcm-gmac.0 has no peer qemu-system-arm: warning: nic npcm-gmac.1 has no peer So suppress those warnings by manually connecting every NIC on the board to some backend. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: David Woodhouse <dwmw@amazon.co.uk> Reviewed-by: Thomas Huth <thuth@redhat.com> Message-id: 20240206171231.396392-3-peter.maydell@linaro.org
2024-02-15tests/qtest/bios-tables-tests: Update virt golden referencePeter Maydell1-2/+0
Update the virt golden reference files to say that the FACP is ACPI v6.3, and the GTDT table is a revision 3 table with space for the virtual EL2 timer. Diffs from iasl: @@ -1,32 +1,32 @@ /* * Intel ACPI Component Architecture * AML/ASL+ Disassembler version 20200925 (64-bit version) * Copyright (c) 2000 - 2020 Intel Corporation * - * Disassembly of tests/data/acpi/virt/FACP, Mon Jan 22 13:48:40 2024 + * Disassembly of /tmp/aml-W8RZH2, Mon Jan 22 13:48:40 2024 * * ACPI Data Table [FACP] * * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue */ [000h 0000 4] Signature : "FACP" [Fixed ACPI Description Table (FADT)] [004h 0004 4] Table Length : 00000114 [008h 0008 1] Revision : 06 -[009h 0009 1] Checksum : 15 +[009h 0009 1] Checksum : 12 [00Ah 0010 6] Oem ID : "BOCHS " [010h 0016 8] Oem Table ID : "BXPC " [018h 0024 4] Oem Revision : 00000001 [01Ch 0028 4] Asl Compiler ID : "BXPC" [020h 0032 4] Asl Compiler Revision : 00000001 [024h 0036 4] FACS Address : 00000000 [028h 0040 4] DSDT Address : 00000000 [02Ch 0044 1] Model : 00 [02Dh 0045 1] PM Profile : 00 [Unspecified] [02Eh 0046 2] SCI Interrupt : 0000 [030h 0048 4] SMI Command Port : 00000000 [034h 0052 1] ACPI Enable Value : 00 [035h 0053 1] ACPI Disable Value : 00 [036h 0054 1] S4BIOS Command : 00 [037h 0055 1] P-State Control : 00 @@ -86,33 +86,33 @@ Use APIC Physical Destination Mode (V4) : 0 Hardware Reduced (V5) : 1 Low Power S0 Idle (V5) : 0 [074h 0116 12] Reset Register : [Generic Address Structure] [074h 0116 1] Space ID : 00 [SystemMemory] [075h 0117 1] Bit Width : 00 [076h 0118 1] Bit Offset : 00 [077h 0119 1] Encoded Access Width : 00 [Undefined/Legacy] [078h 0120 8] Address : 0000000000000000 [080h 0128 1] Value to cause reset : 00 [081h 0129 2] ARM Flags (decoded below) : 0003 PSCI Compliant : 1 Must use HVC for PSCI : 1 -[083h 0131 1] FADT Minor Revision : 00 +[083h 0131 1] FADT Minor Revision : 03 [084h 0132 8] FACS Address : 0000000000000000 [08Ch 0140 8] DSDT Address : 0000000000000000 [094h 0148 12] PM1A Event Block : [Generic Address Structure] [094h 0148 1] Space ID : 00 [SystemMemory] [095h 0149 1] Bit Width : 00 [096h 0150 1] Bit Offset : 00 [097h 0151 1] Encoded Access Width : 00 [Undefined/Legacy] [098h 0152 8] Address : 0000000000000000 [0A0h 0160 12] PM1B Event Block : [Generic Address Structure] [0A0h 0160 1] Space ID : 00 [SystemMemory] [0A1h 0161 1] Bit Width : 00 [0A2h 0162 1] Bit Offset : 00 [0A3h 0163 1] Encoded Access Width : 00 [Undefined/Legacy] [0A4h 0164 8] Address : 0000000000000000 @@ -164,34 +164,34 @@ [0F5h 0245 1] Bit Width : 00 [0F6h 0246 1] Bit Offset : 00 [0F7h 0247 1] Encoded Access Width : 00 [Undefined/Legacy] [0F8h 0248 8] Address : 0000000000000000 [100h 0256 12] Sleep Status Register : [Generic Address Structure] [100h 0256 1] Space ID : 00 [SystemMemory] [101h 0257 1] Bit Width : 00 [102h 0258 1] Bit Offset : 00 [103h 0259 1] Encoded Access Width : 00 [Undefined/Legacy] [104h 0260 8] Address : 0000000000000000 [10Ch 0268 8] Hypervisor ID : 00000000554D4551 Raw Table Data: Length 276 (0x114) - 0000: 46 41 43 50 14 01 00 00 06 15 42 4F 43 48 53 20 // FACP......BOCHS + 0000: 46 41 43 50 14 01 00 00 06 12 42 4F 43 48 53 20 // FACP......BOCHS 0010: 42 58 50 43 20 20 20 20 01 00 00 00 42 58 50 43 // BXPC ....BXPC 0020: 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ 0030: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ 0040: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ 0050: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ 0060: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ 0070: 00 00 10 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ - 0080: 00 03 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 0080: 00 03 00 03 00 00 00 00 00 00 00 00 00 00 00 00 // ................ 0090: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ 00A0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ 00B0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ 00C0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ 00D0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ 00E0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ 00F0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ 0100: 00 00 00 00 00 00 00 00 00 00 00 00 51 45 4D 55 // ............QEMU 0110: 00 00 00 00 // .... @@ -1,32 +1,32 @@ /* * Intel ACPI Component Architecture * AML/ASL+ Disassembler version 20200925 (64-bit version) * Copyright (c) 2000 - 2020 Intel Corporation * - * Disassembly of tests/data/acpi/virt/GTDT, Mon Jan 22 13:48:40 2024 + * Disassembly of /tmp/aml-XDSZH2, Mon Jan 22 13:48:40 2024 * * ACPI Data Table [GTDT] * * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue */ [000h 0000 4] Signature : "GTDT" [Generic Timer Description Table] -[004h 0004 4] Table Length : 00000060 -[008h 0008 1] Revision : 02 -[009h 0009 1] Checksum : 9C +[004h 0004 4] Table Length : 00000068 +[008h 0008 1] Revision : 03 +[009h 0009 1] Checksum : 93 [00Ah 0010 6] Oem ID : "BOCHS " [010h 0016 8] Oem Table ID : "BXPC " [018h 0024 4] Oem Revision : 00000001 [01Ch 0028 4] Asl Compiler ID : "BXPC" [020h 0032 4] Asl Compiler Revision : 00000001 [024h 0036 8] Counter Block Address : FFFFFFFFFFFFFFFF [02Ch 0044 4] Reserved : 00000000 [030h 0048 4] Secure EL1 Interrupt : 0000001D [034h 0052 4] EL1 Flags (decoded below) : 00000000 Trigger Mode : 0 Polarity : 0 Always On : 0 [038h 0056 4] Non-Secure EL1 Interrupt : 0000001E @@ -37,25 +37,28 @@ [040h 0064 4] Virtual Timer Interrupt : 0000001B [044h 0068 4] VT Flags (decoded below) : 00000000 Trigger Mode : 0 Polarity : 0 Always On : 0 [048h 0072 4] Non-Secure EL2 Interrupt : 0000001A [04Ch 0076 4] NEL2 Flags (decoded below) : 00000000 Trigger Mode : 0 Polarity : 0 Always On : 0 [050h 0080 8] Counter Read Block Address : FFFFFFFFFFFFFFFF [058h 0088 4] Platform Timer Count : 00000000 [05Ch 0092 4] Platform Timer Offset : 00000000 +[060h 0096 4] Virtual EL2 Timer GSIV : 00000000 +[064h 0100 4] Virtual EL2 Timer Flags : 00000000 -Raw Table Data: Length 96 (0x60) +Raw Table Data: Length 104 (0x68) - 0000: 47 54 44 54 60 00 00 00 02 9C 42 4F 43 48 53 20 // GTDT`.....BOCHS + 0000: 47 54 44 54 68 00 00 00 03 93 42 4F 43 48 53 20 // GTDTh.....BOCHS 0010: 42 58 50 43 20 20 20 20 01 00 00 00 42 58 50 43 // BXPC ....BXPC 0020: 01 00 00 00 FF FF FF FF FF FF FF FF 00 00 00 00 // ................ 0030: 1D 00 00 00 00 00 00 00 1E 00 00 00 04 00 00 00 // ................ 0040: 1B 00 00 00 00 00 00 00 1A 00 00 00 00 00 00 00 // ................ 0050: FF FF FF FF FF FF FF FF 00 00 00 00 00 00 00 00 // ................ + 0060: 00 00 00 00 00 00 00 00 // ........ Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Ard Biesheuvel <ardb@kernel.org> Message-id: 20240122143537.233498-4-peter.maydell@linaro.org
2024-02-15tests/qtest/bios-tables-test: Allow changes to virt GTDTPeter Maydell1-0/+2
Allow changes to the virt GTDT -- we are going to add the IRQ entry for a new timer to it. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Ard Biesheuvel <ardb@kernel.org> Message-id: 20240122143537.233498-2-peter.maydell@linaro.org
2024-02-15tests/qtest/meson.build: Don't include qtests_npcm7xx in qtests_aarch64Peter Maydell1-1/+0
We deliberately don't include qtests_npcm7xx in qtests_aarch64, because we already get the coverage of those tests via qtests_arm, and we don't want to use extra CI minutes testing them twice. In commit 327b680877b79c4b we added it to qtests_aarch64; revert that change. Fixes: 327b680877b79c4b ("tests/qtest: Creating qtest for GMAC Module") Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 20240206163043.315535-1-peter.maydell@linaro.org
2024-02-07tests/migration-test: Stick with gicv3 in aarch64 testPeter Xu1-1/+1
Recently we introduced cross-binary migration test. It's always wanted that migration-test uses stable guest ABI for both QEMU binaries in this case, so that both QEMU binaries will be compatible on the migration stream with the cmdline specified. Switch to a static gic version "3" rather than using version "max", so that GIC should be stable now across any future QEMU binaries for migration-test. Here the version can actually be anything as long as the ABI is stable. We choose "3" because it's the majority of what we already use in QEMU while still new enough: "git grep gic-version=3" shows 6 hit, while version 4 has no direct user yet besides "max". Note that even with this change, aarch64 won't be able to work yet with migration cross binary test, but then the only missing piece will be the stable CPU model. Reviewed-by: "Daniel P. Berrangé" <berrange@redhat.com> Link: https://lore.kernel.org/r/20240207005403.242235-2-peterx@redhat.com Signed-off-by: Peter Xu <peterx@redhat.com>
2024-02-02Merge tag 'pull-target-arm-20240202' of ↵Peter Maydell3-8/+356
https://git.linaro.org/people/pmaydell/qemu-arm into staging target/arm: fix exception syndrome for AArch32 bkpt insn pci, vmbus, adb, s390x/css-bridge: Switch buses to 3-phase reset system/vl.c: Fix handling of '-serial none -serial something' target/arm: Add ID_AA64ZFR0_EL1.B16B16 to the exposed-to-userspace set tests/qtest/xlnx-versal-trng-test.c: Drop use of variable length array target/arm: Reinstate "vfp" property on AArch32 CPUs doc/sphinx/hxtool.py: add optional label argument to SRST directive hw/arm: Check for CPU types in machine_run_board_init() for various boards pci-host: designware: Limit value range of iATU viewport register hw/arm: Convert some DPRINTF macros to trace events and guest errors hw/arm: NPCM7XX SoC: Add GMAC ethernet controller devices hw/arm: Implement BCM2835 SPI Controller # -----BEGIN PGP SIGNATURE----- # # iQJNBAABCAA3FiEE4aXFk81BneKOgxXPPCUl7RQ2DN4FAmW9C84ZHHBldGVyLm1h # eWRlbGxAbGluYXJvLm9yZwAKCRA8JSXtFDYM3qS6D/wM0/JGEYfaadpuMEOAx4PG # AnfScbPqVhx9J31P2Ks3VrB5F108aq/SaL2BmCb3BLF/ECChlhBXIjd7ukdHstts # F1TvqtvLGDZQz6wSVUeB0YOvAjGa3vIskn+Xvk9e6Ne6PcXgVnxAof/cPsXUiYNy # 6DJjNiLJ/a9Xgq9rjFO6vzW3AL95U6/FmD2F0pOotWXERhNhoyYVV6RtyeqKlDQP # yFVk5h601YURk9PeNZn9zpOpZqjAM7PxyF3X50N3Sv+G0uoKSr6b+c3/fDJbJo3+ # 0LXomEa8hdheQxm1dLY5OD0JX3bvYxwH41bDg9B0iEdjxUdXt6LfXI9Nvw9BAwix # 8AcGJJUaL4XU4uPfHBpRJApM15+MRb0hqfv4ZcGk8e67IIqVeDbKL2clTQGoHSg1 # KaB0POhtFx//M/uBOyk/FR2gb2eBNU8GuoCgxdDwh0K5ylcaK1YPiX4Tcglu4iS0 # Frvazphb2pO1BK6JiJwN2/9ezzDkDJqTKoSqdc4g3ETVOGnxr+tXwcds3t2iK3g2 # y+pgijDOAT3bJO5kYeGvhoEJPKqXwJ3UQ8zTJsU2XSYwBjIyv5V3oOn6elwYJaWq # yUDTC3QEK61KfnQnfTyLfdGWX1aVzHnYLWmQdO+3cczuQU0s0MP246Z1GAgDtgvD # jGjDBz6mryWvP2H0xSmERQ== # =azdP # -----END PGP SIGNATURE----- # gpg: Signature made Fri 02 Feb 2024 15:35:42 GMT # gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE # gpg: issuer "peter.maydell@linaro.org" # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [ultimate] # gpg: aka "Peter Maydell <pmaydell@gmail.com>" [ultimate] # gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [ultimate] # gpg: aka "Peter Maydell <peter@archaic.org.uk>" [ultimate] # Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE * tag 'pull-target-arm-20240202' of https://git.linaro.org/people/pmaydell/qemu-arm: (36 commits) hw/arm: Connect SPI Controller to BCM2835 hw/ssi: Implement BCM2835 SPI Controller tests/qtest: Adding PCS Module test to GMAC Qtest hw/net: GMAC Tx Implementation hw/net: GMAC Rx Implementation tests/qtest: Creating qtest for GMAC Module hw/arm: Add GMAC devices to NPCM7XX SoC hw/net: Add NPCMXXX GMAC device hw/xen: convert stderr prints to error/warn reports hw/xen/xen-hvm-common.c: convert DPRINTF to tracepoints hw/xen/xen-mapcache.c: convert DPRINTF to tracepoints hw/arm/xen_arm.c: convert DPRINTF to trace events and error/warn reports hw/arm/z2: convert DPRINTF to trace events and guest errors hw/arm/strongarm.c: convert DPRINTF to trace events and guest errors pci-host: designware: Limit value range of iATU viewport register hw/arm/zynq: Check for CPU types in machine_run_board_init() hw/arm/vexpress: Check for CPU types in machine_run_board_init() hw/arm/npcm7xx_boards: Simplify setting MachineClass::valid_cpu_types[] hw/arm/musca: Simplify setting MachineClass::valid_cpu_types[] hw/arm/msf2: Simplify setting MachineClass::valid_cpu_types[] ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-02-02hw/arm/npcm7xx: use qemu_configure_nic_device, allow emc0/emc1 as aliasesDavid Woodhouse1-14/+4
Also update the test to specify which device to attach the test socket to, and remove the comment lamenting the fact that we can't do so. Signed-off-by: David Woodhouse <dwmw@amazon.co.uk> Reviewed-by: Thomas Huth <thuth@redhat.com>
2024-02-02tests/qtest: Adding PCS Module test to GMAC QtestNabih Estefan Diaz1-0/+132
- Add PCS Register check to npcm_gmac-test Change-Id: I34821beb5e0b1e89e2be576ab58eabe41545af12 Signed-off-by: Nabih Estefan <nabihestefan@google.com> Reviewed-by: Tyrone Ting <kfting@nuvoton.com> Message-id: 20240131002800.989285-7-nabihestefan@google.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-02-02tests/qtest: Creating qtest for GMAC ModuleNabih Estefan Diaz2-0/+213
- Created qtest to check initialization of registers in GMAC Module. - Implemented test into Build File. Change-Id: I8b2fe152d3987a7eec4cf6a1d25ba92e75a5391d Signed-off-by: Nabih Estefan <nabihestefan@google.com> Reviewed-by: Tyrone Ting <kfting@nuvoton.com> Message-id: 20240131002800.989285-4-nabihestefan@google.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-02-02tests/qtest/xlnx-versal-trng-test.c: Drop use of variable length arrayPeter Maydell1-8/+11
This test program is the last use of any variable length array in the codebase. If we can get rid of all uses of VLAs we can make the compiler error on new additions. This is a defensive measure against security bugs where an on-stack dynamic allocation isn't correctly size-checked (e.g. CVE-2021-3527). In this case the test code didn't even want a variable-sized array, it was just accidentally using syntax that gave it one. (The array size for C has to be an actual constant expression, not just something that happens to be known to be constant...) Remove the VLA usage. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Zhao Liu <zhao1.liu@intel.com> Message-id: 20240125173211.1786196-2-peter.maydell@linaro.org
2024-02-01Merge tag 'pull-aspeed-20240201' of https://github.com/legoater/qemu into ↵Peter Maydell2-0/+206
staging aspeed queue: * Update of buildroot images to 2023.11 (6.6.3 kernel) * Check of the valid CPU type supported by aspeed machines * Simplified models for the IBM's FSI bus and the Aspeed controller bridge # -----BEGIN PGP SIGNATURE----- # # iQIzBAABCAAdFiEEoPZlSPBIlev+awtgUaNDx8/77KEFAmW7Sa8ACgkQUaNDx8/7 # 7KG7mw/8DbMJY6aqgq5YANszzem1ktJphPCNxq081cbczCOUpCNX4aL+0/ANvxxD # lbJQB+SZeIRmuFbxYPhq68rtzB4vG7tsQpns4H33EPKT4vuzF70lq4fgptMiun3q # 1ZJ2LF3jonvQWdhbC17wzAQz0FFb4F7XOxz++UL4okPsgzsYItnd+TWs8q7+erRb # 84UwN+eBTBAl/FiNk679/tBTqAfCVGgQ7dzotr4f3tg5POvrGOrlEjAn0O+dGGDj # wgILmpEBsTsilRB1tz8Kw0j/v/VkHz1DJu45lRAV9CIrN22iKcjMilNGgNDT8kcI # yAlxAw3iN+hVFqDov8wFPjDYd/Qw2oRAPy2Kd14hW9xL8zBOTms1JK5L0PS2+Feo # ZjMJ2cOJq3t4Wt1ZXRhgHfF4ANwP0OZ/y9bHCy3CkBljEeiTQbikHP9gVV4qHXZH # 4Q0HnDZQwAgobw3CmZ8jVx1dQueqy3ycuvkhCyv3S0l/tdbtXDtr5pNNu3dAP/PJ # 3nifLdRImhDvxxO9GKaCdUVLzELzMJl0GrgAsVJPKVnKHA4IiVKmB+XcW9IUbfy/ # 3zA2wHJLrEF+MF6MsuNcEYCCqUvyNLm7rUrXk1wNLXpCJ35bbW5IYy7Ty/8E2GHb # D5Cv/EPNhMBiNA4+HqQlMOTC13Ozv2qwCuWYCh2Ik8mnzaEiyTo= # =0C5S # -----END PGP SIGNATURE----- # gpg: Signature made Thu 01 Feb 2024 07:35:11 GMT # gpg: using RSA key A0F66548F04895EBFE6B0B6051A343C7CFFBECA1 # gpg: Good signature from "Cédric Le Goater <clg@kaod.org>" [undefined] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: A0F6 6548 F048 95EB FE6B 0B60 51A3 43C7 CFFB ECA1 * tag 'pull-aspeed-20240201' of https://github.com/legoater/qemu: hw/fsi: Update MAINTAINER list hw/fsi: Added FSI documentation hw/fsi: Added qtest hw/arm: Hook up FSI module in AST2600 hw/fsi: Aspeed APB2OPB & On-chip peripheral bus hw/fsi: Introduce IBM's FSI master hw/fsi: Introduce IBM's cfam hw/fsi: Introduce IBM's fsi-slave model hw/fsi: Introduce IBM's FSI Bus hw/fsi: Introduce IBM's scratchpad device hw/fsi: Introduce IBM's Local bus hw/arm/aspeed: Check for CPU types in machine_run_board_init() hw/arm/aspeed: Introduce aspeed_soc_cpu_type() helper hw/arm/aspeed: Init CPU defaults in a common helper hw/arm/aspeed: Set default CPU count using aspeed_soc_num_cpus() hw/arm/aspeed: Remove dead code tests/avocado/machine_aspeed.py: Update buildroot images to 2023.11 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-02-01hw/fsi: Added qtestNinad Palsule2-0/+206
Added basic qtests for FSI model. Signed-off-by: Ninad Palsule <ninad@linux.ibm.com> Acked-by: Thomas Huth <thuth@redhat.com> [ clg: aspeed-fsi-test.c -> aspeed_fsi-test.c to match other filenames ] Signed-off-by: Cédric Le Goater <clg@kaod.org>
2024-01-30aspeed: Clean up includesPeter Maydell1-2/+0
This commit was created with scripts/clean-includes. All .c should include qemu/osdep.h first. The script performs three related cleanups: * Ensure .c files include qemu/osdep.h first. * Including it in a .h is redundant, since the .c already includes it. Drop such inclusions. * Likewise, including headers qemu/osdep.h includes is redundant. Drop these, too. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Zhao Liu <zhao1.liu@intel.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
2024-01-29userfaultfd: use 1ULL to build ioctl masksPaolo Bonzini1-2/+2
There is no need to use the Linux-internal __u64 type, 1ULL is guaranteed to be wide enough. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Link: https://lore.kernel.org/r/20240117160313.175609-1-pbonzini@redhat.com Signed-off-by: Peter Xu <peterx@redhat.com>
2024-01-24tests/qtest: Bump timeouts of boot_sector_test()-based tests to 610 secondsThomas Huth1-2/+4
We're still seeing timeouts in qtests that use a TCG payload with TCI on a slow k8s runner: https://gitlab.com/qemu-project/qemu/-/jobs/5990992722 So we should bump the timeout of cdrom-test to see whether that fixes the issue. Now, cdrom-test, as bios-tables-test, pxe-test and vmgenid-test use the boot_sector_test() function for running a TCG payload. That function already uses an internal timeout of 600 seconds with the remark that the test could be slow with TCI. Thus from the outer meson test runner side, we should not use less than 600 seconds as timeout values for these tests. Let's bump them on the meson side to 610 seconds so that the tests themselves can run with their internal 600 seconds timeout and have some additional seconds on top for reporting the outcome. Message-ID: <20240124084412.465638-1-thuth@redhat.com> Reviewed-by: "Daniel P. Berrangé" <berrange@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
2024-01-23tests/qtest: Bump timeout of the boot-serial-test to 360 secondsThomas Huth1-1/+1
On the slow k8s CI runner, the test sometimes takes more than 240 seconds. See for example this run here where it took ~ 267 seconds: https://gitlab.com/qemu-project/qemu/-/jobs/5806087027#L4769 Thus we have to bump the timeout here even further to be on the safe side. Let's use 360 seconds which should hopefully really be high enough now. Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2097 Message-ID: <20240123110353.30658-1-thuth@redhat.com> Reviewed-by: "Daniel P. Berrangé" <berrange@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
2024-01-19hmp: Remove deprecated 'singlestep' commandPhilippe Mathieu-Daudé1-1/+0
This command has been deprecated before the 8.1 release, in commit e9ccfdd91d ("hmp: Add 'one-insn-per-tb' command equivalent to 'singlestep'"). Time to drop it. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: "Dr. David Alan Gilbert" <dave@treblig.org> Reviewed-by: Markus Armbruster <armbru@redhat.com> Message-ID: <20240117151430.29235-3-philmd@linaro.org> Signed-off-by: Thomas Huth <thuth@redhat.com>
2024-01-18Merge tag 'pull-target-arm-20240118' of ↵Peter Maydell3-0/+861
https://git.linaro.org/people/pmaydell/qemu-arm into staging target-arm queue: * docs/devel/docs: Document .hx file syntax * arm_pamax() no longer needs to do feature propagation * docs/system/arm/virt.rst: Improve 'highmem' option docs * STM32L4x5 Implement SYSCFG and EXTI devices * hw/timer: fix systick trace message * hw/arm/virt: Consolidate valid CPU types * load_elf: fix iterator's type for elf file processing # -----BEGIN PGP SIGNATURE----- # # iQJNBAABCAA3FiEE4aXFk81BneKOgxXPPCUl7RQ2DN4FAmWpHM4ZHHBldGVyLm1h # eWRlbGxAbGluYXJvLm9yZwAKCRA8JSXtFDYM3pZxD/sGIXvTeoOCsum7OFpArKoQ # J+wcy74pO526IDzjudgtwP8kFW09oVblMPgrt/68F9LY4Oa7sDNAZX/Xqlhs/hdJ # SVbOXArRmyLvgLpn8KVii9xk9iI/olMGt0S6KcXAErdgFud+JcCevbS0D5fAF4Ua # /G/4ldnwr+WcYUA5IIoi02ymSBm5VNeH2bKu0MPS3xpizjzgOFxWTBYwq3zkZYWD # w5GjH9+F+IC67CiAlCLvuQBqpGLdRwFBttU05hLtGXuSlnvS+FtJTooI7gGD17CR # 2wTa7qF716qDN1lNSIvxA6t8/dWNMIYCZYdlxJml476WzP3jECpth2WFWqE0G3yg # Orr7sFVB8X6JmtlR34srW6e3CZA3t+4FIWqcdELFLi5IQtJeer90jqQ9xwx4SttJ # nsHdy5M8txWSa61yAaDTXMID/smVlC7sWTKJrR9kV7v5+b9OPQ/R8k0mCODl5Aer # mzAVuCvUQVYK3j7fzprGrlldla57s3v78OAhqACLgKflK0+aJSJjglulPrSMK1z5 # bRPS5jLZjFwEi2VaLVg3LPJiBMDj1s/wAl0ycfCQSv2oEzvmpkw+Ar1HDc2NFe+d # 9dunbdhAZJMwh+ABIg7iMj+l0ncOXDa4DS+6BnjRxfECCa172u3viq1HATkLLAFI # GTkcJ5hIQzNEeg9ob0MDIg== # =Rfpe # -----END PGP SIGNATURE----- # gpg: Signature made Thu 18 Jan 2024 12:42:54 GMT # gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE # gpg: issuer "peter.maydell@linaro.org" # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [ultimate] # gpg: aka "Peter Maydell <pmaydell@gmail.com>" [ultimate] # gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [ultimate] # gpg: aka "Peter Maydell <peter@archaic.org.uk>" [ultimate] # Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE * tag 'pull-target-arm-20240118' of https://git.linaro.org/people/pmaydell/qemu-arm: load_elf: fix iterator's type for elf file processing hw/arm/virt: Consolidate valid CPU types hw/timer: fix systick trace message tests/qtest: Add STM32L4x5 SYSCFG QTest testcase hw/arm: Connect STM32L4x5 SYSCFG to STM32L4x5 SoC hw/misc: Implement STM32L4x5 SYSCFG tests/qtest: Add STM32L4x5 EXTI QTest testcase hw/arm: Connect STM32L4x5 EXTI to STM32L4x5 SoC hw/misc: Implement STM32L4x5 EXTI docs/system/arm/virt.rst: Improve 'highmem' option docs target/arm: arm_pamax() no longer needs to do feature propagation docs/devel/docs: Document .hx file syntax Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-01-18Merge tag 'pull-request-2024-01-16' of https://gitlab.com/thuth/qemu into ↵Peter Maydell2-3/+5
staging * Improve the timeouts for some problematic qtests * Enable some ROP mitigation compiler switches # -----BEGIN PGP SIGNATURE----- # # iQJFBAABCAAvFiEEJ7iIR+7gJQEY8+q5LtnXdP5wLbUFAmWmNDURHHRodXRoQHJl # ZGhhdC5jb20ACgkQLtnXdP5wLbVM0w/+Nafbtnw9Q1gp633CIYQRsNDGiKiCND5H # epLfd3DFAG2jATZm/hIIrV3dlEkGRQh916XKik572eUm2yyu3i3EqVNooTcLr0k/ # 4MI1ZzG0rnAnAr15zVdUaDCiaGdlpcSGTwLDAlQjIR4n0MdugQ/bkrfkDRU0YD/6 # mv/yDck5fHOUDm88LA7Gxep0G7U8Wi8oiQXx+WlbQpmDHfBJM7ERQSPhXobtVtFO # 8wpceUcMwlGBecxEsRggrRhdn09CJUyuirP8UHG4rT8xMjkXpqHJVqZ+gVDyV65J # y9y6snCk+oFyCTDSstQxVbzHg/1C4xE2gVUMaXv4Wu1TcCgBpF1WDQymXb35Buuh # pbgAaF1ZsBGwE7rUUJIF3NBTpjmedP4NbCR2EPsiL06w08mG7IRuU/b8JStuAHef # qUqxiHfpEwAxXY8O83XOvBb+zJ625OQHGi/MGDnaYczBfqBJAx2AKiuSmMWBAWo2 # gO4kQX25sPzov6xsLcjEwh0HcJ9W5mkGRJ/x8GSjWnvDlGBDBYWPUShJlohDKGU0 # 4+JGk4+8RKMoKE97bO8DItOp9ahh87up/qHDFkJJo+VKuDaBPdzlS6PURzc8wv0T # QquWUkfdE6qYIPr8ShVYT00NNThIKLyn0qaN4s1mQ+2h8p8nXc4aYsWgcr2wxJFm # sOoVvwOXzDE= # =Yuwq # -----END PGP SIGNATURE----- # gpg: Signature made Tue 16 Jan 2024 07:45:57 GMT # gpg: using RSA key 27B88847EEE0250118F3EAB92ED9D774FE702DB5 # gpg: issuer "thuth@redhat.com" # gpg: Good signature from "Thomas Huth <th.huth@gmx.de>" [full] # gpg: aka "Thomas Huth <thuth@redhat.com>" [full] # gpg: aka "Thomas Huth <huth@tuxfamily.org>" [full] # gpg: aka "Thomas Huth <th.huth@posteo.de>" [unknown] # Primary key fingerprint: 27B8 8847 EEE0 2501 18F3 EAB9 2ED9 D774 FE70 2DB5 * tag 'pull-request-2024-01-16' of https://gitlab.com/thuth/qemu: meson: mitigate against use of uninitialize stack for exploits meson: mitigate against ROP exploits with -fzero-call-used-regs qtest: Bump npcm7xx_watchdog_timer-test timeout to 2 minutes tests/qtest/npcm7xx_watchdog_timer: Only test the corner cases by default tests/qtest/meson.build: Bump the boot-serial-test timeout to 4 minutes Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-01-16qtest: Bump npcm7xx_watchdog_timer-test timeout to 2 minutesThomas Huth1-0/+1
The npcm7xx_watchdog_timer-test can take more than 60 seconds in SPEED=slow mode on a loaded host system. Bumping to 2 minutes will give more headroom. Message-ID: <20240112164717.1063954-1-thuth@redhat.com> Reviewed-by: "Daniel P. Berrangé" <berrange@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
2024-01-16tests/qtest/npcm7xx_watchdog_timer: Only test the corner cases by defaultThomas Huth1-2/+3
The test_prescaler() part in the npcm7xx_watchdog_timer test is quite repetitive, testing all possible combinations of the WTCLK and WTIS bitfields. Since each test spins up a new instance of QEMU, this is rather an expensive test, especially on loaded host systems. For the normal quick test mode, it should be sufficient to test the corner settings of these fields (i.e. 0 and 3), so we can speed up this test in the default mode quite a bit. Message-ID: <20240115070223.30178-1-thuth@redhat.com> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Thomas Huth <thuth@redhat.com>
2024-01-16tests/qtest/meson.build: Bump the boot-serial-test timeout to 4 minutesThomas Huth1-1/+1
When running with TCI, the boot-serial-test can take longer than 3 minutes: https://gitlab.com/qemu-project/qemu/-/jobs/5890481086#L4774 Bump the timeout to 4 minutes to avoid CI failures here. Message-ID: <20240115071146.31213-1-thuth@redhat.com> Reviewed-by: "Daniel P. Berrangé" <berrange@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
2024-01-16tests/qtest: Re-enable multifd cancel testFabiano Rosas1-8/+2
We've found the source of flakiness in this test, so re-enable it. Reviewed-by: Juan Quintela <quintela@redhat.com> Signed-off-by: Fabiano Rosas <farosas@suse.de> Link: https://lore.kernel.org/r/20230606144551.24367-4-farosas@suse.de [peterx: rebase to 2a61a6964c, to use migration_test_add()] Signed-off-by: Peter Xu <peterx@redhat.com>
2024-01-16tests/qtest/migration: Use the new migration_test_addFabiano Rosas1-103/+112
Replace the tests registration with the new function that prints tests names. Signed-off-by: Fabiano Rosas <farosas@suse.de> Reviewed-by: Peter Xu <peterx@redhat.com> Link: https://lore.kernel.org/r/20240104142144.9680-8-farosas@suse.de Signed-off-by: Peter Xu <peterx@redhat.com>
2024-01-16tests/qtest/migration: Add a wrapper to print test namesFabiano Rosas2-0/+33
Our usage of gtest results in us losing the very basic functionality of "knowing which test failed". The issue is that gtest only prints test names ("paths" in gtest parlance) once the test has finished, but we use asserts in the tests and crash gtest itself before it can print anything. We also use a final abort when the result of g_test_run is not 0. Depending on how the test failed/broke we can see the function that trigged the abort, which may be representative of the test, but it could also just be some generic function. We have been relying on the primitive method of looking at the name of the previous successful test and then looking at the code to figure out which test should have come next. Add a wrapper to the test registration that does the job of printing the test name before running. Signed-off-by: Fabiano Rosas <farosas@suse.de> Reviewed-by: Peter Xu <peterx@redhat.com> Link: https://lore.kernel.org/r/20240104142144.9680-7-farosas@suse.de Signed-off-by: Peter Xu <peterx@redhat.com>
2024-01-16tests/qtest/migration: Print migration incoming errorsFabiano Rosas1-0/+6
We're currently just asserting when incoming migration fails. Let's print the error message from QMP as well. Signed-off-by: Fabiano Rosas <farosas@suse.de> Reviewed-by: Peter Xu <peterx@redhat.com> Link: https://lore.kernel.org/r/20240104142144.9680-6-farosas@suse.de Signed-off-by: Peter Xu <peterx@redhat.com>
2024-01-15tests/qtest: Add STM32L4x5 SYSCFG QTest testcaseInès Varhol2-1/+333
Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Acked-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Arnaud Minier <arnaud.minier@telecom-paris.fr> Signed-off-by: Inès Varhol <ines.varhol@telecom-paris.fr> Message-id: 20240109194438.70934-4-ines.varhol@telecom-paris.fr Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-01-15tests/qtest: Add STM32L4x5 EXTI QTest testcaseInès Varhol2-0/+529
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Acked-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Arnaud Minier <arnaud.minier@telecom-paris.fr> Signed-off-by: Inès Varhol <ines.varhol@telecom-paris.fr> Message-id: 20240109160658.311932-4-ines.varhol@telecom-paris.fr Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-01-12Merge tag 'pull-testing-updates-120124-2' of https://gitlab.com/stsquad/qemu ↵Peter Maydell1-12/+13
into staging testing and misc updates - add LE microblaze test to avocado - use modern snapshot=on to avoid trashing disk image - use plain bool for fe_is_open - various updates to qtest timeouts - enable meson test timeouts - tweak the readthedocs environment - partially revert un-flaking x86_64 # -----BEGIN PGP SIGNATURE----- # # iQEzBAABCgAdFiEEZoWumedRZ7yvyN81+9DbCVqeKkQFAmWhPccACgkQ+9DbCVqe # KkS5agf+OoW6HOitt34YeL6cGGtIKaxbta+Fs6jq+ucIbN63TmLTuKrmPiRNxjuo # Fj2Qvh9R7Tl7Q/a7ZAym0Fze7GtsvvsidkiQS4pmi9vYuJrhS734CxXHT8JS6zJr # ymQ0nGZODg1cVB4oAR9sXo/OwEQdDTSgKp8wdNr930fxYwokUKBUgcOqElu3SWHv # duSYDuaflnP5B8ZGbb1ZnOlwS9lZIHTwjZyN5J1YtxF0T8Ez4A+xseEOpQ/00MoE # Ecjdp3ELCxzOI+1U33Yni7ol//fxQpRKi+xf2fGIxhuSA3i32rmY5NWTvl7VwuS1 # gXryjX2rukSujySP3vkdtTp0dmkbpg== # =ZuDd # -----END PGP SIGNATURE----- # gpg: Signature made Fri 12 Jan 2024 13:25:27 GMT # gpg: using RSA key 6685AE99E75167BCAFC8DF35FBD0DB095A9E2A44 # gpg: Good signature from "Alex Bennée (Master Work Key) <alex.bennee@linaro.org>" [full] # Primary key fingerprint: 6685 AE99 E751 67BC AFC8 DF35 FBD0 DB09 5A9E 2A44 * tag 'pull-testing-updates-120124-2' of https://gitlab.com/stsquad/qemu: (22 commits) tests/avocado: partially revert unmasking of replay_linux tests readthodocs: fully specify a build environment mtest2make: stop disabling meson test timeouts tests/fp: Bump fp-test-mulAdd test timeout to 3 minutes tests/unit: Bump test-crypto-block test timeout to 5 minutes tests/unit: Bump test-aio-multithread test timeout to 2 minutes tests/qtest: Bump the device-introspect-test timeout to 12 minutes qtest: bump bios-table-test timeout to 9 minutes qtest: bump aspeed_smc-test timeout to 6 minutes qtest: bump qos-test timeout to 2 minutes qtest: bump boot-serial-test timeout to 3 minutes qtest: bump prom-env-test timeout to 6 minutes qtest: bump pxe-test timeout to 10 minutes qtest: bump test-hmp timeout to 4 minutes qtest: bump npcm7xx_pwm-test timeout to 5 minutes qtest: bump qom-test timeout to 15 minutes qtest: bump migration-test timeout to 8 minutes qtest: bump min meson timeout to 60 seconds chardev: use bool for fe_is_open gitlab: include microblazeel in testing ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-01-12tests/qtest: Bump the device-introspect-test timeout to 12 minutesThomas Huth1-0/+1
When running the test in slow mode on a very loaded system with the arm/aarch64 target and with --enable-debug, it can take longer than 10 minutes to finish the introspection test. Bump the timeout to twelve minutes to make sure that it also finishes in such situations. Signed-off-by: Thomas Huth <thuth@redhat.com> Message-Id: <20231215070357.10888-13-thuth@redhat.com> Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
2024-01-12qtest: bump bios-table-test timeout to 9 minutesDaniel P. Berrangé1-1/+1
This is reliably hitting the current 2 minute timeout in GitLab CI, and for the TCI job, it even hits a 6 minute timeout. Reviewed-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Daniel P. Berrangé <berrange@redhat.com> Message-ID: <20230717182859.707658-12-berrange@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com> Message-Id: <20231215070357.10888-12-thuth@redhat.com> Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
generated by cgit v1.1 at 2025-09-25 10:14:47 +0000