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2024-09-28Merge tag 'pull-request-2024-09-25' of https://gitlab.com/thuth/qemu into ↵Peter Maydell1-1/+0
staging * Convert more Avocado tests to the new functional test framework * Clean up assert() statements, use g_assert_not_reached() when possible * Improve output of the gitlab CI jobs # -----BEGIN PGP SIGNATURE----- # # iQJFBAABCAAvFiEEJ7iIR+7gJQEY8+q5LtnXdP5wLbUFAmbz7xgRHHRodXRoQHJl # ZGhhdC5jb20ACgkQLtnXdP5wLbWm6A//eVn+tzyyKCX/xdXlf7XyVpezvRpTFPOS # HyO0WMkCf2kGmu6qYKx/fDZg86opdQzPLH2gPkuVrGOMZ0Z2630DjH0jNih8lL9Q # J1oRX5YlU92chlzNmq59WB/j9CKd91ILtOoaPBuZkDob57yGEYVzCPqetVvF7L2+ # +rbnccrNPumGJFt035fxUGiGfgsmp28MHQzDwQdyr38uGjyNlqvqidfC8Vj1qzqP # B7HvhGB/vkF0eHaanMt2el/ZuLKf+qeCi//F/CiXGMYnuKXyShA/Db6xvMElw1jB # aQdwphP71IO+cxjJLaNjDHKGFstArsM/E21qlaSTBi+FTmPiwVULpVTiBmWsjhOh # /klpdgRHf0hL2MciYKyOWgjlTocx3rEKjCTe2U5tpta9fp9CrlgMQotjDZIbohGI # ULNahrW3Zmg4EmXDApfhYMXsQsSgWas9QSkmxzJzDp0VC7tf2Oq7RxeySrlw9MCx # OG2qQY+rNcJ3NnpATjfAJpT1kg/IahDOCNHfLEaj1u13XVQIthVADvHwy5WxbwRP # mwp3V9e9sUoznkM2eV646lzmkMim/WdYBF0YpT7eBs80+GoXZ0thx9IqWmwzX/ox # rndBczVN+RY6PydJP40yljdvS7ArRT73wHqL6yKHfDpvFc4/p5mxTWwLQ3yJbXbE # T3I+wtgfBU8= # =FH7b # -----END PGP SIGNATURE----- # gpg: Signature made Wed 25 Sep 2024 12:08:08 BST # gpg: using RSA key 27B88847EEE0250118F3EAB92ED9D774FE702DB5 # gpg: issuer "thuth@redhat.com" # gpg: Good signature from "Thomas Huth <th.huth@gmx.de>" [full] # gpg: aka "Thomas Huth <thuth@redhat.com>" [full] # gpg: aka "Thomas Huth <huth@tuxfamily.org>" [full] # gpg: aka "Thomas Huth <th.huth@posteo.de>" [unknown] # Primary key fingerprint: 27B8 8847 EEE0 2501 18F3 EAB9 2ED9 D774 FE70 2DB5 * tag 'pull-request-2024-09-25' of https://gitlab.com/thuth/qemu: (44 commits) .gitlab-ci.d: Make separate collapsible log sections for build and test .gitlab-ci.d: Split build and test in cross build job templates scripts/checkpatch.pl: emit error when using assert(false) tests/qtest: remove return after g_assert_not_reached() qom: remove return after g_assert_not_reached() qobject: remove return after g_assert_not_reached() migration: remove return after g_assert_not_reached() hw/ppc: remove return after g_assert_not_reached() hw/pci: remove return after g_assert_not_reached() hw/net: remove return after g_assert_not_reached() hw/hyperv: remove return after g_assert_not_reached() include/qemu: remove return after g_assert_not_reached() tcg/loongarch64: remove break after g_assert_not_reached() fpu: remove break after g_assert_not_reached() target/riscv: remove break after g_assert_not_reached() target/arm: remove break after g_assert_not_reached() hw/tpm: remove break after g_assert_not_reached() hw/scsi: remove break after g_assert_not_reached() hw/net: remove break after g_assert_not_reached() hw/acpi: remove break after g_assert_not_reached() ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-09-27Merge tag 'pull-tcg-20240922' of https://gitlab.com/rth7680/qemu into stagingPeter Maydell17-407/+748
target/ppc: Fix lxvx/stxvx facility check linux-user: update syscall_nr.h to Linux v6.10 linux-user: update syscall.tbl to Linux v6.11 tcg: Fix iteration step in 32-bit gvec operation tcg: Propagate new TCGOp to add_as_label_use tcg/*: Do not expand cmp_vec, cmpsel_vec early tcg/optimize: Fold movcond with true and false values identical tcg/optimize: Optimize cmp_vec and cmpsel_vec tcg/optimize: Optimize bitsel_vec tcg/i386: Optimize cmpsel with constant 0 operand 3. tcg/i386: Implement cmp_vec with avx512 insns tcg/i386: Implement cmpsel_vec with avx512 insns tcg/i386: Implement vector TST{EQ,NE} for avx512 tcg/ppc: Implement cmpsel_vec and optimize with constant 0/-1 arguments tcg/s390x: Implement cmpsel_vec and optimize with constant 0/-1 arguments # -----BEGIN PGP SIGNATURE----- # # iQFQBAABCgA7FiEEekgeeIaLTbaoWgXAZN846K9+IV8FAmbwBsIdHHJpY2hhcmQu # aGVuZGVyc29uQGxpbmFyby5vcmcACgkQZN846K9+IV/bzwf40V8fsRhfc8u/k2Xw # +bXyfyX7ydgB+82YoO71+Wy15ntmYmbL/6O9kGuJXWX8HRDrAR8Js9zDgveysw5m # m/EG+XAbVjYhjaoaaz2nfr+5auQoos9NoCji3s3UJln6sCuZ2Enl0DTFluoHZfgr # /YVAghJ4dwH0hfzO9kmsKmJ9I19HugMMN4dNvEcjQyDDUhgGGjkUaRtGNxwuiwuf # ArL2XhFauXgloryDmpUKQ0BJJ0t8rdPlaRJ8dHqJUnJwav0TW3QVXbrs8gOkmmbg # 9plYTC9DlTguQobvapCDVjiGy/6yuSF/AUpcdQbTRtTi3BrzhTydfLlOtI64GtaQ # OBKd # =ID/g # -----END PGP SIGNATURE----- # gpg: Signature made Sun 22 Sep 2024 13:00:02 BST # gpg: using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E215F # gpg: issuer "richard.henderson@linaro.org" # gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>" [full] # Primary key fingerprint: 7A48 1E78 868B 4DB6 A85A 05C0 64DF 38E8 AF7E 215F * tag 'pull-tcg-20240922' of https://gitlab.com/rth7680/qemu: (31 commits) linux-user: update syscall.tbl to Linux v6.11 linux-user,loongarch: move to syscalltbl file linux-user,hexagon: move to syscalltbl file linux-user,riscv: move to syscalltbl file linux-user,openrisc: move to syscalltbl file linux-user,aarch64: move to syscalltbl file linux-user: update syscall.tbl to Linux v6.10 linux-user, mips: update syscall-args-o32.c.inc to Linux v6.10 linux-user: update syscall_nr.h to Linux v6.10 target/ppc: Fix lxvx/stxvx facility check tcg/s390x: Optimize cmpsel with constant 0/-1 arguments tcg/s390x: Implement cmpsel_vec tcg/ppc: Optimize cmpsel with constant 0/-1 arguments tcg/ppc: Implement cmpsel_vec tcg/i386: Implement vector TST{EQ,NE} for avx512 tcg/i386: Implement cmpsel_vec with avx512 insns tcg/i386: Add predicate parameters to tcg_out_evex_opc tcg/i386: Implement cmp_vec with avx512 insns tcg/i386: Optimize cmpsel with constant 0 operand 3. tcg/optimize: Optimize bitsel_vec ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-09-24tcg/loongarch64: remove break after g_assert_not_reached()Pierrick Bouvier1-1/+0
This patch is part of a series that moves towards a consistent use of g_assert_not_reached() rather than an ad hoc mix of different assertion mechanisms. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Message-ID: <20240919044641.386068-25-pierrick.bouvier@linaro.org> Signed-off-by: Thomas Huth <thuth@redhat.com>
2024-09-22tcg/s390x: Optimize cmpsel with constant 0/-1 argumentsRichard Henderson3-10/+34
These can be simplified to and/or/andc/orc, avoiding the load of the constantinto a register. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2024-09-22tcg/s390x: Implement cmpsel_vecRichard Henderson3-20/+23
Do not allow cmpsel_vec to be expanded early, so that we can make the correct decision wrt the sense of the comparison. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2024-09-22tcg/ppc: Optimize cmpsel with constant 0/-1 argumentsRichard Henderson2-12/+33
These can be simplified to and/or/andc/orc, avoiding the load of the constantinto a register. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2024-09-22tcg/ppc: Implement cmpsel_vecRichard Henderson3-9/+54
Do not allow cmpsel_vec to be expanded early, so that we can make the correct decision wrt the sense of the comparison. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2024-09-22tcg/i386: Implement vector TST{EQ,NE} for avx512Richard Henderson2-4/+29
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2024-09-22tcg/i386: Implement cmpsel_vec with avx512 insnsRichard Henderson1-1/+43
The avx512 vpblendm* instructions exactly implement cmpsel, using a predicate input. Of course this matches nicely with the avx512 predicate comparison instructions. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2024-09-22tcg/i386: Add predicate parameters to tcg_out_evex_opcRichard Henderson1-2/+4
Extend tcg_out_evex_opc to handle the predicate and zero-merging parameters of the evex prefix. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2024-09-22tcg/i386: Implement cmp_vec with avx512 insnsRichard Henderson1-1/+63
The sse/avx instruction set only has EQ and GT as direct comparisons. Other signed comparisons can be generated from swapping and inversion. However unsigned comparisons are not available and must be transformed to signed comparisons by biasing the inputs. The avx512 instruction set has a complete set of comparisons, with results placed into a predicate register. We can produce the normal cmp_vec result by using VPMOVM2*. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2024-09-22tcg/i386: Optimize cmpsel with constant 0 operand 3.Richard Henderson3-8/+27
These can be simplified to and/andc, avoiding the load of the zero into a register. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2024-09-22tcg/optimize: Optimize bitsel_vecRichard Henderson1-0/+58
Fold matching true/false operands. Fold true/false operands with 0/-1 to simpler logicals. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2024-09-22tcg/optimize: Optimize cmp_vec and cmpsel_vecRichard Henderson1-0/+36
Place immediate values second in the comparison. Place destination matches first in the true/false values. All of this mirrors what we do for integer setcond and movcond. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2024-09-22tcg/optimize: Fold movcond with true and false values identicalRichard Henderson1-0/+5
Fold "x = cond ? y : y" to "x = y". Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2024-09-22tcg/s390x: Do not expand cmp_vec earlyRichard Henderson1-74/+65
Move expansion to opcode generation. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2024-09-22tcg/ppc: Do not expand cmp_vec earlyRichard Henderson1-79/+90
Move expansion to opcode generation. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2024-09-22tcg/i386: Do not expand cmpsel_vec earlyRichard Henderson4-34/+52
Expand during output instead of during opcode generation. Remove x86_vpblendvb_vec opcode, this this removes the only user. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2024-09-22tcg/i386: Do not expand cmp_vec earlyRichard Henderson1-123/+100
Move most of expansion to opcode generation, leaving the conversion of unsigned to signed to be done in the early phase. Small inefficiencies, but not incorrect results, are introduced until cmpsel_vec is converted in the next patch. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2024-09-22tcg/i386: Split out tcg_out_vex_modrm_typeRichard Henderson1-23/+15
Helper function to handle setting of VEXL based on the type of the operation. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2024-09-22tcg: Export vec_gen_6Richard Henderson2-2/+4
Add declaration to tcg-internal.h, making it available for use from tcg backend vector expanders. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2024-09-22tcg: Fix iteration step in 32-bit gvec operationTANG Tiancheng1-1/+1
The loop in the 32-bit case of the vector compare operation was incorrectly incrementing by 8 bytes per iteration instead of 4 bytes. This caused the function to process only half of the intended elements. Cc: qemu-stable@nongnu.org Fixes: 9622c697d1 (tcg: Add gvec compare with immediate and scalar operand) Signed-off-by: TANG Tiancheng <tangtiancheng.ttc@alibaba-inc.com> Reviewed-by: Liu Zhiwei <zhiwei_liu@linux.alibaba.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-ID: <20240904142739.854-2-zhiwei_liu@linux.alibaba.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2024-09-22tcg: Propagate new TCGOp to add_as_label_useRichard Henderson1-31/+32
The use of tcg_last_op does not interact well with TCGContext.emit_before_op, resulting in the label being linked to something other than the branch op. In this case it is easier to simply collect the emitted branch op and pass it directly to add_as_label_use. Reported-by: Elisha Hollander <just4now666666@gmail.com> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2024-09-22tcg: Return TCGOp from tcg_gen_op[1-6]Richard Henderson2-14/+21
TCGOp to be propagated further in the next patch. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2024-09-19plugins: save value during memory accessesPierrick Bouvier1-7/+59
Different code paths handle memory accesses: - tcg generated code - load/store helpers - atomic helpers This value is saved in cpu->neg.plugin_mem_value_{high,low}. Values are written only for accessed word size (upper bits are not set). Atomic operations are doing read/write at the same time, so we generate two memory callbacks instead of one, to allow plugins to access distinct values. For now, we can have access only up to 128 bits, thus split this in two 64 bits words. When QEMU will support wider operations, we'll be able to reconsider this. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Message-Id: <20240724194708.1843704-2-pierrick.bouvier@linaro.org> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20240916085400.1046925-5-alex.bennee@linaro.org>
2024-08-08tcg/ppc: Sync tcg_out_test and constraintsRichard Henderson1-11/+10
Ensure the code structure is the same for matching constraints and emitting code, lest we allow constants that cannot be trivially tested. Cc: qemu-stable@nongnu.org Fixes: ad788aebbab ("tcg/ppc: Support TCG_COND_TST{EQ,NE}") Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2487 Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <44328324-af73-4439-9d2b-d414e0e13dd7@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2024-07-04Merge tag 'for-upstream' of https://gitlab.com/bonzini/qemu into stagingRichard Henderson1-4/+4
* meson: Pass objects and dependencies to declare_dependency(), not static_library() * meson: Drop the .fa library suffix * target/i386: drop AMD machine check bits from Intel CPUID * target/i386: add avx-vnni-int16 feature * target/i386: SEV bugfixes * target/i386: SEV-SNP -cpu host support * char: fix exit issues # -----BEGIN PGP SIGNATURE----- # # iQFIBAABCAAyFiEE8TM4V0tmI4mGbHaCv/vSX3jHroMFAmaGceoUHHBib256aW5p # QHJlZGhhdC5jb20ACgkQv/vSX3jHroNcpgf/XziKojGOTvYsE7xMijOUswYjCG5m # ZVLqxTug8Q0zO/9mGvluKBTWmh8KhRWOovX5iZL8+F0gPoYPG4ONpNhh3wpA9+S7 # H7ph4V6sDJBX4l3OrOK6htD8dO5D9kns1iKGnE0lY60PkcHl+pU8BNWfK1zYp5US # geiyzuRFRRtDmoNx5+o+w+D+W5msPZsnlj5BnPWM+O/ykeFfSrk2ztfdwHKXUhCB # 5FJcu2sWVx+wsdVzdjgT8USi5+VTK4vabq3SfccmNRxBRnJOCU5MrR63stMDceo4 # TswSB88I0WRV1848AudcGZRkjvKaXLyHJ+QTjg2dp7itEARJ3MGsvOpS5A== # =3kv7 # -----END PGP SIGNATURE----- # gpg: Signature made Thu 04 Jul 2024 02:56:58 AM PDT # gpg: using RSA key F13338574B662389866C7682BFFBD25F78C7AE83 # gpg: issuer "pbonzini@redhat.com" # gpg: Good signature from "Paolo Bonzini <bonzini@gnu.org>" [full] # gpg: aka "Paolo Bonzini <pbonzini@redhat.com>" [full] * tag 'for-upstream' of https://gitlab.com/bonzini/qemu: target/i386/SEV: implement mask_cpuid_features target/i386: add support for masking CPUID features in confidential guests char-stdio: Restore blocking mode of stdout on exit target/i386: add avx-vnni-int16 feature i386/sev: Fallback to the default SEV device if none provided in sev_get_capabilities() i386/sev: Fix error message in sev_get_capabilities() target/i386: do not include undefined bits in the AMD topoext leaf target/i386: SEV: fix formatting of CPUID mismatch message target/i386: drop AMD machine check bits from Intel CPUID target/i386: pass X86CPU to x86_cpu_get_supported_feature_word meson: Drop the .fa library suffix Revert "meson: Propagate gnutls dependency" meson: Pass objects and dependencies to declare_dependency() meson: merge plugin_ldflags into emulator_link_args meson: move block.syms dependency out of libblock meson: move shared_module() calls where modules are already walked Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2024-07-03tcg/optimize: Fix TCG_COND_TST* simplification of setcond2Richard Henderson1-1/+1
Argument ordering for setcond2 is: output, a_low, a_high, b_low, b_high, cond The test is supposed to be against b_low, not a_high. Cc: qemu-stable@nongnu.org Fixes: ceb9ee06b71 ("tcg/optimize: Handle TCG_COND_TST{EQ,NE}") Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2413 Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Tested-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20240701024623.1265028-1-richard.henderson@linaro.org>
2024-07-03util/cpuinfo-riscv: Support host/cpuinfo.h for riscvRichard Henderson2-101/+29
Move detection code out of tcg, similar to other hosts. Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2024-07-03meson: Drop the .fa library suffixPaolo Bonzini1-2/+0
The non-standard .fa library suffix breaks the link source de-duplication done by Meson so drop it. The lack of link source de-duplication causes AddressSanitizer to complain ODR violations, and makes GNU ld abort when combined with clang's LTO. Fortunately, the non-standard suffix is not necessary anymore for two reasons. First, the non-standard suffix was necessary for fork-fuzzing. Meson wraps all standard-suffixed libraries with --start-group and --end-group. This made a fork-fuzz.ld linker script wrapped as well and broke builds. Commit d2e6f9272d33 ("fuzz: remove fork-fuzzing scaffolding") dropped fork-fuzzing so we can now restore the standard suffix. Second, the libraries are not even built anymore, because it is possible to just use the object files directly via extract_all_objects(). The occurences of the suffix were detected and removed by performing a tree-wide search with 'fa' and .fa (note the quotes and dot). Signed-off-by: Akihiko Odaki <akihiko.odaki@daynix.com> Message-ID: <20240524-xkb-v4-4-2de564e5c859@daynix.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2024-07-03meson: Pass objects and dependencies to declare_dependency()Akihiko Odaki1-2/+4
We used to request declare_dependency() to link_whole static libraries. If a static library is a thin archive, GNU ld keeps all object files referenced by the archive open, and sometimes exceeds the open file limit. Another problem with link_whole is that suboptimal handling of nested dependencies. link_whole by itself does not propagate dependencies. In particular, gnutls, a dependency of crypto, is not propagated to its users, and we currently workaround the issue by declaring gnutls as a dependency for each crypto user. On the other hand, if you write something like libfoo = static_library('foo', 'foo.c', dependencies: gnutls) foo = declare_dependency(link_whole: libfoo) libbar = static_library('bar', 'bar.c', dependencies: foo) bar = declare_dependency(link_whole: libbar, dependencies: foo) executable('prog', sources: files('prog.c'), dependencies: [foo, bar]) hoping to propagate the gnutls dependency into bar.c, you'll see a linking failure for "prog", because the foo.c.o object file is included in libbar.a and therefore it is linked twice into "prog": once from libfoo.a and once from libbar.a. Here Meson does not see the duplication, it just asks the linker to link all of libfoo.a and libbar.a into "prog". Instead of using link_whole, extract objects included in static libraries and pass them to declare_dependency(); and then the dependencies can be added as well so that they are propagated, because object files on the linker command line are always deduplicated. This requires Meson 1.1.0 or later. Signed-off-by: Akihiko Odaki <akihiko.odaki@daynix.com> Message-ID: <20240524-objects-v1-1-07cbbe96166b@daynix.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2024-06-28Revert "host/i386: assume presence of POPCNT"Paolo Bonzini1-2/+3
This reverts commit 45ccdbcb24baf99667997fac5cf60318e5e7db51. The x86-64 instruction set can now be tuned down to x86-64 v1 or i386 Pentium Pro. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2024-06-19tcg/loongarch64: Fix tcg_out_movi vs some pcrel pointersRichard Henderson1-17/+15
Simplify the logic for two-part, 32-bit pc-relative addresses. Rather than assume all such fit in int32_t, do some arithmetic and assert a result, do some arithmetic first and then check to see if the pieces are in range. Cc: qemu-stable@nongnu.org Fixes: dacc51720db ("tcg/loongarch64: Implement tcg_out_mov and tcg_out_movi") Reviewed-by: Song Gao <gaosong@loongson.cn> Reported-by: Song Gao <gaosong@loongson.cn> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2024-06-19tcg/loongarch64: Enable v256 with LASXRichard Henderson2-1/+4
Reviewed-by: Song Gao <gaosong@loongson.cn> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2024-06-19tcg/loongarch64: Support LASX in tcg_out_vec_opRichard Henderson1-84/+135
Reviewed-by: Song Gao <gaosong@loongson.cn> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2024-06-19tcg/loongarch64: Split out vdvjukN in tcg_out_vec_opRichard Henderson1-25/+31
Fixes a bug in the immediate shifts, because the exact encoding depends on the element size. Reviewed-by: Song Gao <gaosong@loongson.cn> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2024-06-19tcg/loongarch64: Remove temp_vec from tcg_out_vec_opRichard Henderson1-5/+4
Use TCG_VEC_TMP0 directly. Reviewed-by: Song Gao <gaosong@loongson.cn> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2024-06-19tcg/loongarch64: Support LASX in tcg_out_{mov,ld,st}Richard Henderson1-0/+19
Reviewed-by: Song Gao <gaosong@loongson.cn> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2024-06-19tcg/loongarch64: Split out vdvjvk in tcg_out_vec_opRichard Henderson1-56/+63
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2024-06-19tcg/loongarch64: Support LASX in tcg_out_addsub_vecRichard Henderson1-16/+20
Reviewed-by: Song Gao <gaosong@loongson.cn> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2024-06-19tcg/loongarch64: Simplify tcg_out_addsub_vecRichard Henderson1-14/+15
Reviewed-by: Song Gao <gaosong@loongson.cn> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2024-06-19tcg/loongarch64: Support LASX in tcg_out_dupi_vecRichard Henderson1-1/+6
Reviewed-by: Song Gao <gaosong@loongson.cn> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2024-06-19tcg/loongarch64: Use tcg_out_dup_vec in tcg_out_dupi_vecRichard Henderson1-17/+1
Reviewed-by: Song Gao <gaosong@loongson.cn> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2024-06-19tcg/loongarch64: Support LASX in tcg_out_dupm_vecRichard Henderson1-6/+24
Each element size has a different encoding, so code cannot be shared in the same way as with tcg_out_dup_vec. Reviewed-by: Song Gao <gaosong@loongson.cn> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2024-06-19tcg/loongarch64: Support LASX in tcg_out_dup_vecRichard Henderson1-3/+7
Reviewed-by: Song Gao <gaosong@loongson.cn> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2024-06-19tcg/loongarch64: Simplify tcg_out_dup_vecRichard Henderson1-16/+6
Reviewed-by: Song Gao <gaosong@loongson.cn> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2024-06-19tcg/loongarch64: Support TCG_TYPE_V64Richard Henderson2-3/+7
We can implement this with fld_d, fst_d for load and store, and then use the normal v128 operations in registers. This will improve support for guests which use v64. Reviewed-by: Song Gao <gaosong@loongson.cn> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2024-06-19tcg/loongarch64: Handle i32 and i64 moves between gr and frRichard Henderson1-5/+17
Reviewed-by: Song Gao <gaosong@loongson.cn> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2024-06-19tcg/loongarch64: Use fp load/store for I32 and I64 into vector regsRichard Henderson1-26/+10
Reviewed-by: Song Gao <gaosong@loongson.cn> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2024-06-19tcg/loongarch64: Import LASX, FP insnsRichard Henderson1-3542/+1607
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
generated by cgit v1.1 at 2024-12-28 16:00:16 +0000