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2024-05-06tcg/optimize: Optimize setcond with zmaskRichard Henderson1-0/+110
If we can show that high bits of an input are zero, then we may optimize away some comparisons. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2024-05-06tcg/i386: Optimize setcond of TST{EQ,NE} with 0xffffffffRichard Henderson1-2/+15
This may be treated as a 32-bit EQ/NE comparison against 0, which is in turn treated as a LTU/GEU comparison against 1. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2024-05-06tcg/i386: Simplify immediate 8-bit logical vector shiftsRichard Henderson1-46/+13
The x86 isa does not have this operation, so we need an expansion. Use the same algorithm that we use for expanding this vector operation with integers: perform the shift with a wider type and then mask the bits that must be zero. This reduces the instruction count from 5 to 2. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2024-05-06tcg: Add write_aofs to GVecGen3iRichard Henderson1-8/+22
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2024-04-30plugins: Replace pr_ops with a proper debug dump flagRichard Henderson1-1/+28
The DEBUG_PLUGIN_GEN_OPS ifdef is replaced with "-d op_plugin". The second pr_ops call can be obtained with "-d op". Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2024-04-30tcg: Remove INDEX_op_plugin_cb_{start,end}Richard Henderson1-10/+0
These opcodes are no longer used. Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2024-04-30tcg: Remove TCG_CALL_PLUGINRichard Henderson1-3/+1
Since we no longer emit plugin helpers during the initial code translation phase, we don't need to specially mark plugin helpers. Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2024-04-30plugins: Use emit_before_op for PLUGIN_GEN_FROM_MEMRichard Henderson2-3/+8
Introduce a new plugin_mem_cb op to hold the address temp and meminfo computed by tcg-op-ldst.c. Because this now has its own opcode, we no longer need PLUGIN_GEN_FROM_MEM. Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2024-04-30plugins: Use emit_before_op for PLUGIN_GEN_AFTER_INSNRichard Henderson1-0/+5
Introduce a new plugin_cb op and migrate one operation. By using emit_before_op, we do not need to emit opcodes early and modify them later -- we can simply emit the final set of opcodes once. Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2024-04-30tcg: Pass function pointer to tcg_gen_call*Richard Henderson1-21/+24
For normal helpers, read the function pointer from the structure earlier. For plugins, this will allow the function pointer to come from elsewhere. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2024-04-30tcg: Make tcg/helper-info.h self-containedRichard Henderson1-0/+1
Move MAX_CALL_IARGS from tcg.h and include for the define of TCG_TARGET_REG_BITS. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2024-04-26exec: Rename 'exec/user/guest-base.h' as 'user/guest-base.h'Philippe Mathieu-Daudé1-1/+1
The include/user/ directory contains the user-emulation specific headers. Move guest-base.h there too. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Anton Johansson <anjo@rev.ng> Message-Id: <20240418192525.97451-15-philmd@linaro.org>
2024-04-09tcg: Add TCGContext.emit_before_opRichard Henderson1-2/+12
Allow operations to be emitted via normal expanders into the middle of the opcode stream. Tested-by: Jørgen Hansen <Jorgen.Hansen@wdc.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2024-04-09tcg/optimize: Do not attempt to constant fold neg_vecRichard Henderson1-9/+8
Split out the tail of fold_neg to fold_neg_no_const so that we can avoid attempting to constant fold vector negate. Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2150 Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2024-03-29tcg/optimize: Fix sign_mask for logical right-shiftRichard Henderson1-1/+1
The 'sign' computation is attempting to locate the sign bit that has been repeated, so that we can test if that bit is known zero. That computation can be zero if there are no known sign repetitions. Cc: qemu-stable@nongnu.org Fixes: 93a967fbb57 ("tcg/optimize: Propagate sign info for shifting") Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2248 Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2024-03-12tcg/aarch64: Fix tcg_out_brcond for test comparisonsRichard Henderson1-0/+1
When converting test vs UINT32_MAX to compare vs 0, we need to adjust the condition to match. Fixes: 34aff3c2e06 ("tcg/aarch64: Generate CBNZ for TSTNE of UINT32_MAX") Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2024-03-12tcg/aarch64: Fix tcg_out_cmp for test comparisonsRichard Henderson1-2/+1
Pass the type to tcg_out_logicali; remove the assert, duplicated at the start of tcg_out_logicali. Fixes: 339adf2f38e ("tcg/aarch64: Support TCG_COND_TST{EQ,NE}") Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Michael Tokarev <mjt@tls.msk.ru> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2024-02-29tcg/optimize: fix uninitialized variablePaolo Bonzini1-1/+2
The variables uext_opc and sext_opc are used without initialization if TCG_TARGET_extract_i{32,64}_valid returns false. The result, depending on the compiler, might be the generation of extract and sextract opcodes with invalid offset and count, or just random data in the TCG opcode stream. Fixes: ceb9ee06b71 ("tcg/optimize: Handle TCG_COND_TST{EQ,NE}", 2024-02-03) Cc: Richard Henderson <pbonzini@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <20240228110641.287205-1-pbonzini@redhat.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2024-02-29tcg/aarch64: Apple does not align __int128_t in even registersRichard Henderson1-1/+5
From https://developer.apple.com/documentation/xcode/writing-arm64-code-for-apple-platforms When passing an argument with 16-byte alignment in integer registers, Apple platforms allow the argument to start in an odd-numbered xN register. The standard ABI requires it to begin in an even-numbered xN register. Cc: qemu-stable@nongnu.org Fixes: 5427a9a7604 ("tcg: Add TCG_TARGET_CALL_{RET,ARG}_I128") Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2169 Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <9fc0c2c7-dd57-459e-aecb-528edb74b4a7@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2024-02-13tcg/arm: Fix goto_tb for large translation blocksRichard Henderson1-2/+2
Correct arithmetic for separating high and low on a large negative number. Cc: qemu-stable@nongnu.org Fixes: 79ffece4447 ("tcg/arm: Implement direct branch for goto_tb") Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1714 Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Michael Tokarev <mjt@tls.msk.ru>
2024-02-05tcg/tci: Support TCG_COND_TST{EQ,NE}Richard Henderson2-1/+15
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2024-02-05tcg/s390x: Support TCG_COND_TST{EQ,NE}Richard Henderson2-44/+97
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2024-02-03tcg/s390x: Add TCG_CT_CONST_CMPRichard Henderson3-21/+58
Better constraint for tcg_out_cmp, based on the comparison. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2024-02-03tcg/s390x: Split constraint A into J+URichard Henderson3-23/+23
Signed 33-bit == signed 32-bit + unsigned 32-bit. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2024-02-03tcg/ppc: Support TCG_COND_TST{EQ,NE}Richard Henderson2-9/+115
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2024-02-03tcg/ppc: Add TCG_CT_CONST_CMPRichard Henderson3-10/+44
Better constraint for tcg_out_cmp, based on the comparison. We can't yet remove the fallback to load constants into a scratch because of tcg_out_cmp2, but that path should not be as frequent. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2024-02-03tcg/ppc: Tidy up tcg_target_const_matchRichard Henderson1-11/+16
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2024-02-03tcg/ppc: Use cr0 in tcg_to_bc and tcg_to_iselRichard Henderson1-34/+34
Using cr0 means we could choose to use rc=1 to compute the condition. Adjust the tables and tcg_out_cmp that feeds them. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2024-02-03tcg/ppc: Sink tcg_to_bc usage into tcg_out_bcRichard Henderson1-11/+17
Rename the current tcg_out_bc function to tcg_out_bc_lab, and create a new function that takes an integer displacement + link. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2024-02-03tcg/sparc64: Support TCG_COND_TST{EQ,NE}Richard Henderson2-3/+15
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2024-02-03tcg/sparc64: Pass TCGCond to tcg_out_cmpRichard Henderson1-10/+11
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2024-02-03tcg/sparc64: Hoist read of tcg_cond_to_rcondRichard Henderson1-11/+14
Use a non-zero value here (an illegal encoding) as a better condition than is_unsigned_cond for when MOVR/BPR is usable. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2024-02-03tcg/i386: Use TEST r,r to test 8/16/32 bitsPaolo Bonzini1-0/+17
Just like when testing against the sign bits, TEST r,r can be used when the immediate is 0xff, 0xff00, 0xffff, 0xffffffff. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2024-02-03tcg/i386: Improve TSTNE/TESTEQ vs powers of twoRichard Henderson3-8/+53
Use "test x,x" when the bit is one of the 4 sign bits. Use "bt imm,x" otherwise. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2024-02-03tcg/i386: Support TCG_COND_TST{EQ,NE}Richard Henderson2-37/+60
Merge tcg_out_testi into tcg_out_cmp and adjust the two uses. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2024-02-03tcg/i386: Move tcg_cond_to_jcc[] into tcg_out_cmpRichard Henderson1-11/+13
Return the x86 condition codes to use after the compare. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2024-02-03tcg/i386: Pass x86 condition codes to tcg_out_cmovRichard Henderson1-8/+8
Hoist the tcg_cond_to_jcc index outside the function. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2024-02-03tcg/arm: Support TCG_COND_TST{EQ,NE}Richard Henderson2-2/+29
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20231028194522.245170-12-richard.henderson@linaro.org> [PMD: Split from bigger patch, part 2/2] Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <20231108145244.72421-2-philmd@linaro.org>
2024-02-03tcg/arm: Split out tcg_out_cmp()Richard Henderson1-15/+17
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20231028194522.245170-12-richard.henderson@linaro.org> [PMD: Split from bigger patch, part 1/2] Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <20231108145244.72421-1-philmd@linaro.org>
2024-02-03tcg/aarch64: Generate CBNZ for TSTNE of UINT32_MAXRichard Henderson1-0/+6
... and the inverse, CBZ for TSTEQ. Suggested-by: Paolo Bonzini <pbonzini@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2024-02-03tcg/aarch64: Generate TBZ, TBNZRichard Henderson1-12/+62
Test the sign bit for LT/GE vs 0, and TSTNE/EQ vs a power of 2. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <20240119224737.48943-2-philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2024-02-03tcg/aarch64: Massage tcg_out_brcond()Philippe Mathieu-Daudé1-8/+23
In order to ease next commit review, modify tcg_out_brcond() to switch over TCGCond. No logical change intended. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <20240119224737.48943-1-philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2024-02-03tcg/aarch64: Support TCG_COND_TST{EQ,NE}Richard Henderson4-19/+43
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2024-02-03tcg: Add TCGConst argument to tcg_target_const_matchRichard Henderson11-12/+52
Fill the new argument from any condition within the opcode. Not yet used within any backend. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2024-02-03tcg/optimize: Lower TCG_COND_TST{EQ,NE} if unsupportedRichard Henderson3-9/+55
After having performed other simplifications, lower any remaining test comparisons with AND. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2024-02-03tcg/optimize: Handle TCG_COND_TST{EQ,NE}Richard Henderson1-22/+218
Fold constant comparisons. Canonicalize "tst x,x" to equality vs zero. Canonicalize "tst x,sign" to sign test vs zero. Fold double-word comparisons with zero parts. Fold setcond of "tst x,pow2" to a bit extract. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2024-02-03tcg/optimize: Do swap_commutative2 in do_constant_folding_cond2Richard Henderson1-50/+57
Mirror the new do_constant_folding_cond1 by doing all argument and condition adjustment within one helper. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2024-02-03tcg/optimize: Split out do_constant_folding_cond1Richard Henderson1-30/+27
Handle modifications to the arguments and condition in a single place. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2024-02-03tcg/optimize: Split out arg_is_const_valRichard Henderson1-15/+23
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2024-02-03tcg: Introduce TCG_TARGET_HAS_tstRichard Henderson10-0/+20
Define as 0 for all tcg backends. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
generated by cgit v1.1 at 2024-08-17 19:19:59 +0000