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2010-03-14tcg: declare internal helpers as const and pureAurelien Jarno1-4/+9
TCG internal helpers only access to the values passed in arguments, and do not modify the CPU internal state. Thus they can be declared as const and pure. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-03-14tcg/arm: use helpers for divu/remuAurelien Jarno2-95/+0
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-03-14tcg: add div/rem 32-bit helpersAurelien Jarno6-2/+65
Some targets like ARM would benefit to use 32-bit helpers for div/rem/divu/remu. Create a #define for div2 so that targets can select between div, div2 and helper implementation. Use the helper version if none of the #define are present. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-03-13Fix build with -DNDEBUG in CFLAGSBlue Swirl1-1/+1
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2010-03-13tcg/arm: implement andc opAurelien Jarno2-1/+5
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-03-13tcg: update README with const and pure helpersAurelien Jarno1-4/+7
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-03-13tcg/arm: correctly save/restore registers in prologue/epilogueAurelien Jarno1-4/+7
Since commit 6113d6d3169393c323ac4c82d756a850145a5e7a QEMU crashes on ARM hosts. This is not a bug of this commit, but a latent bug revealed by this commit. The TCG code is called through a procedure call using the prologue and epilogue code. This code does not save and restore enough registers. The "Procedure Call Standard for the ARM Architecture" says: A subroutine must preserve the contents of the registers r4-r8, r10,  r11 and SP (and r9 in PCS variants that designate r9 as v6). The current code only saves and restores r9 to r11, and misses r4 to r8. The patch fixes that by saving r4 to r12. Theoretically there is no need to save and restore r12, but an even number of registers have to be saved as per EABI. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-03-13Fix Sparc host build breakageBlue Swirl1-0/+8
Fix error: CC sparc-bsd-user/op_helper.o In file included from /src/qemu/tcg/tcg.c:158: /src/qemu/tcg/sparc/tcg-target.c:728:5: "TARGET_PHYS_ADDR_BITS" is not defined Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2010-03-13tcg/ppc[64]: Only define addend load helpers in softmmu casemalc2-0/+5
Signed-off-by: malc <av1474@comtv.ru>
2010-03-12Remove TLB from userspacePaul Brook3-0/+6
Remove TLB from userspace CPU structure. Signed-off-by: Paul Brook <paul@codesourcery.com>
2010-03-02tcg/arm: merge the two sets of #define for optional opsAurelien Jarno1-14/+5
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-03-02tcg/arm: accept immediate arguments for brcond/setcondAurelien Jarno1-6/+20
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Andrzej Zaborowski <andrew.zaborowski@intel.com>
2010-03-02Add a missing breakAndrzej Zaborowski1-0/+1
2010-03-02tcg/arm: implement setcond2Aurelien Jarno1-0/+11
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Andrzej Zaborowski <andrew.zaborowski@intel.com>
2010-03-02tcg/arm: implement setcondAurelien Jarno1-0/+9
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Andrzej Zaborowski <andrew.zaborowski@intel.com>
2010-03-02tcg/arm: fix div2/divu2Aurelien Jarno1-6/+24
When restoring register values, increase the stack register for skipped values. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Andrzej Zaborowski <andrew.zaborowski@intel.com>
2010-02-27tcg/ppc: Fix right rotationmalc1-1/+2
Signed-off-by: malc <av1474@comtv.ru>
2010-02-23tcg/ppc: Fix typomalc1-1/+1
Signed-off-by: malc <av1474@comtv.ru>
2010-02-22tcg/ppc64: Use C90 style commentsmalc1-18/+18
Signed-off-by: malc <av1474@comtv.ru>
2010-02-22tcg/ppc: Implement some of the optional opsmalc2-8/+88
Signed-off-by: malc <av1474@comtv.ru>
2010-02-22tcg: fix build on 32-bit hppa, ppc and sparc hostsJay Foad3-3/+4
The qemu_ld32s op is only defined if TCG_TARGET_REG_BITS == 64. Signed-off-by: Jay Foad <jay.foad@gmail.com> Signed-off-by: malc <av1474@comtv.ru>
2010-02-20tcg: fix assertion with --enable-debugJay Foad1-5/+0
On 32-bit hosts op_qemu_ld32s is unused. Remove it to fix the following assertion failure: qemu-alpha: tcg/tcg.c:1055: tcg_add_target_add_op_defs: Assertion `tcg_op_defs[op].used' failed. Signed-off-by: Jay Foad <jay.foad@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2010-02-20tcg: Add comments for all optional instructions not implemented.Richard Henderson8-17/+106
Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2010-02-20tcg-sparc: Implement ORC.Richard Henderson2-0/+7
Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2010-02-20tcg-sparc: Implement ANDC.Richard Henderson2-0/+8
Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2010-02-20tcg: Optional target implementation of ORC.Richard Henderson2-0/+17
Previously ORC was always implemented by tcg-op.h with an explicit NOT opcode. Allow a target implementation. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2010-02-20tcg: Optional target implementation of ANDC.Richard Henderson2-0/+17
Previously ANDC was always implemented by tcg-op.h with an explicit NOT opcode. Allow a target implementation. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2010-02-20tcg-sparc: Implement not.Richard Henderson2-0/+8
The fallback implementation of "ret = arg1 ^ -1" isn't ideal because of the extra tcg op to load the minus one. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2010-02-20tcg-sparc: Implement neg.Richard Henderson2-2/+16
The fallback implementation of "ret = 0 - arg1" isn't ideal, first because of the extra tcg op to load the zero, and second because we fail to handle zero as %g0 for arg1 of the sub. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2010-02-20tcg/ppc: Consistently use calling convention selection macrosmalc1-12/+12
Signed-off-by: malc <av1474@comtv.ru>
2010-02-20Use ppc host calling convention definitions to set ↵Juergen Lock1-3/+3
TCG_TARGET_CALL_{ALIGN_ARGS,STACK_OFFSET}. New version after malc's comments. (This avoids having to do #if defined __linux__ || defined __FreeBSD__ || defined __FreeBSD_kernel__ for the third case.) Submitted by: Andreas Tobler <andreast@fgznet.ch> (original version) Signed-off-by: Juergen Lock <nox@jelal.kn-bremen.de> Signed-off-by: malc <av1474@comtv.ru>
2010-02-18tcg: Add consistency checks for op definitionsStefan Weil2-0/+24
When compiled with CONFIG_DEBUG_TCG, this code looks for missing, duplicate and wrong entries in the op definitions. Errors will raise an assertion at program start (all checks are done in the initial phase). The current code contains such errors, at least for i386 guest on i386 host. Signed-off-by: Stefan Weil <weil@mail.berlios.de> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2010-02-16tcg-sparc: Implement setcond, setcond2.Richard Henderson1-0/+127
Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2010-02-16tcg: Add tcg_swap_cond.Richard Henderson1-0/+8
Returns the condition as if with swapped comparison operands. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2010-02-09tcg/mips: fix crash in tcg_out_qemu_ld()Aurelien Jarno1-2/+2
The address register is overriden when it corresponds to v0 and the fast path is taken, which leads to a crash. Fix that by using the a0 register instead. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-02-09tcg/mips: implement setcond2Aurelien Jarno1-12/+80
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-02-08tcg/mips: implement setcondAurelien Jarno1-0/+65
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-02-08tcg: move setcond* ops to non-optional sectionAurelien Jarno1-35/+37
setcond is not an optional op, move it to the non-optional section. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-02-08tcg: add setcondi pseudo-opAurelien Jarno1-0/+18
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-02-07tcg/ppc64: implement setcondmalc1-0/+133
Signed-off-by: malc <av1474@comtv.ru>
2010-02-07tcg/ppc32: proper setcond implementationmalc1-25/+25
Signed-off-by: malc <av1474@comtv.ru>
2010-02-07tcg/ppc32: implement setcond[2]malc1-14/+157
Signed-off-by: malc <av1474@comtv.ru>
2010-02-06tcg-i386: Implement setcond.Richard Henderson1-3/+70
Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-02-06tcg-i386: Implement small forward branches.Richard Henderson1-38/+79
There are places, like brcond2, where we know that the destination of a forward branch will be within 127 bytes. Add the R_386_PC8 relocation type to support this. Add a flag to tcg_out_jxx and tcg_out_brcond* to enable it. Set the flag in the brcond2 label_next branches; pass along the input flag otherwise. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-02-06tcg-x86_64: implement setcondRichard Henderson1-5/+33
Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-02-06tcg: add tcg_invert_condRichard Henderson1-0/+5
It is very handy to have a reliable mapping of a condition to its inverse. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-02-06tcg: generic support for conditional setRichard Henderson4-6/+78
Defines setcond_{i32,i64} and setcond2_i32 for 64-on-32-bit. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-02-06tcg: document double-word support opcodes.Richard Henderson1-0/+23
The internal opcodes brcond2, add2, sub2, mulu2 were undocumented. Place these in a new section that clearly indicates that they are not to be emitted by translators. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-01-15tcg/x86_64: Avoid unnecessary REX.B prefixes.Richard Henderson1-16/+30
The existing P_REXB internal opcode flag unconditionally emits the REX prefix. Technically it's not needed if the register in question is %al, %bl, %cl, %dl. Eliding the prefix requires splitting the P_REXB flag into two, in order to indicate whether the byte register in question is in the REG or the R/M field. Within TCG, the byte register is in the REG field only for stores. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-01-14tcg/x86_64: Special-case all 32-bit AND operands.Richard Henderson1-18/+8
This avoids an unnecessary REX.W prefix when dealing with AND operands that fit into a 32-bit quantity. The most common change actually seen is movz[wb]q -> movz[wb]l. Similarly, avoid REXW in ext{8,16}u_i64 tcg opcodes. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
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