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2019-01-28tcg/riscv: enable dynamic TLB sizingRichard Henderson2-71/+55
2019-01-28tcg/s390: enable dynamic TLB sizingRichard Henderson2-27/+20
2019-01-28tcg/sparc: enable dynamic TLB sizingRichard Henderson2-33/+51
2019-01-28tcg/ppc: enable dynamic TLB sizingRichard Henderson2-44/+55
2019-01-28tcg/aarch64: enable dynamic TLB sizingRichard Henderson2-42/+60
2019-01-28tcg/i386: enable dynamic TLB sizingEmilio G. Cota2-15/+15
2019-01-28tcg: introduce dynamic TLB sizingEmilio G. Cota9-0/+9
2019-01-28tcg/aarch64: Implement vector minmax arithmeticRichard Henderson2-1/+25
2019-01-28tcg/aarch64: Implement vector saturating arithmeticRichard Henderson2-1/+25
2019-01-28tcg/i386: Implement vector minmax arithmeticRichard Henderson2-1/+82
2019-01-28tcg/i386: Implement vector saturating arithmeticRichard Henderson2-1/+43
2019-01-28tcg/i386: Split subroutines out of tcg_expand_vec_opRichard Henderson1-219/+224
2019-01-28tcg: Add opcodes for vector minmax arithmeticRichard Henderson10-0/+164
2019-01-28tcg: Add opcodes for vector saturated arithmeticRichard Henderson9-24/+119
2019-01-28tcg: Add write_aofs to GVecGen4Richard Henderson2-8/+21
2019-01-28tcg: Add gvec expanders for nand, nor, eqvRichard Henderson4-0/+81
2019-01-28tcg: Add logical simplifications during gvec expandRichard Henderson1-5/+30
2019-01-11avoid TABs in files that only contain a fewPaolo Bonzini1-2/+2
2019-01-11qemu/queue.h: simplify reverse access to QTAILQPaolo Bonzini2-4/+4
2019-01-11qemu/queue.h: leave head structs anonymous unless necessaryPaolo Bonzini1-1/+1
2018-12-26tcg: Improve call argument loadingRichard Henderson1-1/+2
2018-12-26tcg: Record register preferences during livenessRichard Henderson1-32/+165
2018-12-26tcg: Add TCG_OPF_BB_EXITRichard Henderson3-10/+16
2018-12-26tcg: Split out more subroutines from liveness_pass_1Richard Henderson1-12/+23
2018-12-26tcg: Rename and adjust liveness_pass_1 helpersRichard Henderson1-8/+5
2018-12-26tcg: Reindent parts of liveness_pass_1Richard Henderson1-67/+70
2018-12-26tcg: Dump register preference info with livenessRichard Henderson2-10/+37
2018-12-26tcg: Improve register allocation for matching constraintsRichard Henderson1-12/+24
2018-12-26tcg: Add output_pref to TCGOpRichard Henderson2-7/+14
2018-12-26tcg: Add preferred_reg argument to tcg_reg_alloc_do_moviRichard Henderson1-4/+5
2018-12-26tcg: Add preferred_reg argument to temp_syncRichard Henderson1-8/+8
2018-12-26tcg: Add preferred_reg argument to temp_loadRichard Henderson1-9/+9
2018-12-26tcg: Add preferred_reg argument to tcg_reg_allocRichard Henderson1-22/+81
2018-12-26tcg: Add reachable_code_passRichard Henderson1-0/+76
2018-12-26tcg: Reference count labelsRichard Henderson4-1/+25
2018-12-26tcg: Add TCG_CALL_NO_RETURNRichard Henderson1-0/+2
2018-12-26tcg: Renumber TCG_CALL_* flagsRichard Henderson1-3/+3
2018-12-26tcg/riscv: Add the target init codeAlistair Francis1-0/+31
2018-12-26tcg/riscv: Add the prologue generation and register the JITAlistair Francis1-0/+111
2018-12-26tcg/riscv: Add the out op decoderAlistair Francis1-0/+496
2018-12-26tcg/riscv: Add direct load and store instructionsAlistair Francis1-0/+158
2018-12-26tcg/riscv: Add slowpath load and store instructionsAlistair Francis1-0/+256
2018-12-26tcg/riscv: Add branch and jump instructionsAlistair Francis1-0/+145
2018-12-26tcg/riscv: Add the add2 and sub2 instructionsAlistair Francis1-0/+55
2018-12-26tcg/riscv: Add the out load and store instructionsAlistair Francis1-0/+65
2018-12-26tcg/riscv: Add the extract instructionsAlistair Francis1-0/+34
2018-12-26tcg/riscv: Add the mov and movi instructionAlistair Francis1-0/+86
2018-12-26tcg/riscv: Add the relocation functionsAlistair Francis1-0/+88
2018-12-26tcg/riscv: Add the instruction emittersAlistair Francis1-0/+48
2018-12-26tcg/riscv: Add the immediate encodersAlistair Francis1-0/+90
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