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Files
Lines
2021-02-02
tcg: Remove TCG_TARGET_CON_SET_H
Richard Henderson
1
-1
/
+0
2021-02-02
tcg/riscv: Split out constraint sets to tcg-target-con-set.h
Richard Henderson
3
-60
/
+54
2021-02-02
tcg: Remove TCG_TARGET_CON_STR_H
Richard Henderson
1
-1
/
+0
2021-02-02
tcg/riscv: Split out target constraints to tcg-target-con-str.h
Richard Henderson
3
-39
/
+35
2021-01-13
tcg: Remove movi and dupi opcodes
Richard Henderson
1
-2
/
+0
2021-01-07
tcg: Constify TCGLabelQemuLdst.raddr
Richard Henderson
1
-2
/
+1
2021-01-07
tcg: Constify tcg_code_gen_epilogue
Richard Henderson
1
-2
/
+1
2021-01-07
tcg: Remove TCG_TARGET_SUPPORT_MIRROR
Richard Henderson
1
-1
/
+0
2021-01-07
tcg/riscv: Support split-wx code generation
Richard Henderson
2
-19
/
+24
2021-01-07
tcg/riscv: Remove branch-over-branch fallback
Richard Henderson
1
-50
/
+6
2021-01-07
tcg/riscv: Fix branch range checks
Richard Henderson
1
-13
/
+15
2021-01-07
tcg: Add --accel tcg,split-wx property
Richard Henderson
1
-0
/
+1
2021-01-07
tcg: Adjust tb_target_set_jmp_target for split-wx
Richard Henderson
1
-1
/
+1
2021-01-07
tcg: Adjust tcg_register_jit for const
Richard Henderson
1
-1
/
+1
2021-01-07
tcg: Adjust tcg_out_call for const
Richard Henderson
1
-3
/
+3
2021-01-07
tcg: Move tcg epilogue pointer out of TCGContext
Richard Henderson
1
-2
/
+2
2021-01-07
tcg: Introduce INDEX_op_qemu_st8_i32
Richard Henderson
1
-0
/
+1
2021-01-06
Merge remote-tracking branch 'remotes/bonzini-gitlab/tags/for-upstream' into ...
Peter Maydell
1
-5
/
+0
2021-01-04
tcg/riscv: Fix illegal shift instructions
Zihao Yu
1
-6
/
+6
2021-01-02
util: Extract flush_icache_range to cacheflush.c
Richard Henderson
1
-5
/
+0
2020-10-08
tcg: Remove TCG_CT_REG
Richard Henderson
1
-2
/
+0
2020-10-08
tcg: Drop union from TCGArgConstraint
Richard Henderson
1
-7
/
+7
2020-08-21
meson: rename included C source files to .c.inc
Paolo Bonzini
1
-2
/
+2
2020-07-13
tcg/riscv: Remove superfluous breaks
Liao Pingfang
1
-2
/
+0
2020-01-15
tcg: Search includes in the parent source directory
Philippe Mathieu-Daudé
1
-2
/
+2
2019-09-03
tcg: TCGMemOp is now accelerator independent MemOp
Tony Nguyen
1
-10
/
+10
2019-07-09
tcg/riscv: Fix RISC-VH host build failure
Alistair Francis
1
-2
/
+2
2019-06-10
cpu: Move the softmmu tlb to CPUNegativeOffsetState
Richard Henderson
1
-24
/
+7
2019-06-10
tcg: Create struct CPUTLB
Richard Henderson
1
-10
/
+2
2019-05-13
tcg: Return bool success from tcg_out_mov
Richard Henderson
1
-2
/
+3
2019-04-24
tcg: Restart TB generation after out-of-line ldst overflow
Richard Henderson
1
-4
/
+12
2019-04-24
tcg: Add INDEX_op_extract2_{i32,i64}
Richard Henderson
1
-0
/
+2
2019-01-28
cputlb: Remove static tlb sizing
Richard Henderson
1
-1
/
+0
2019-01-28
tcg/riscv: enable dynamic TLB sizing
Richard Henderson
2
-71
/
+55
2019-01-28
tcg: introduce dynamic TLB sizing
Emilio G. Cota
1
-0
/
+1
2018-12-26
tcg/riscv: Add the target init code
Alistair Francis
1
-0
/
+31
2018-12-26
tcg/riscv: Add the prologue generation and register the JIT
Alistair Francis
1
-0
/
+111
2018-12-26
tcg/riscv: Add the out op decoder
Alistair Francis
1
-0
/
+496
2018-12-26
tcg/riscv: Add direct load and store instructions
Alistair Francis
1
-0
/
+158
2018-12-26
tcg/riscv: Add slowpath load and store instructions
Alistair Francis
1
-0
/
+256
2018-12-26
tcg/riscv: Add branch and jump instructions
Alistair Francis
1
-0
/
+145
2018-12-26
tcg/riscv: Add the add2 and sub2 instructions
Alistair Francis
1
-0
/
+55
2018-12-26
tcg/riscv: Add the out load and store instructions
Alistair Francis
1
-0
/
+65
2018-12-26
tcg/riscv: Add the extract instructions
Alistair Francis
1
-0
/
+34
2018-12-26
tcg/riscv: Add the mov and movi instruction
Alistair Francis
1
-0
/
+86
2018-12-26
tcg/riscv: Add the relocation functions
Alistair Francis
1
-0
/
+88
2018-12-26
tcg/riscv: Add the instruction emitters
Alistair Francis
1
-0
/
+48
2018-12-26
tcg/riscv: Add the immediate encoders
Alistair Francis
1
-0
/
+90
2018-12-26
tcg/riscv: Add support for the constraints
Alistair Francis
1
-0
/
+168
2018-12-26
tcg/riscv: Add the tcg target registers
Alistair Francis
1
-0
/
+118
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